Thermal Simulation into the Effect of Varying Encapsulant Media on Wire Bond Stress Under Temperature Cycling

2018 ◽  
Author(s):  
Matt Packwood ◽  
Daohui Li ◽  
Paul Mumby-Croft ◽  
Xiaoping Dai
Keyword(s):  
Thermal Simulation ◽  
Temperature Cycling ◽  
Bond Stress ◽  
Wire Bond

Combined Temperature and Vibration Testing for Wire Bond Interconnections in Harsh Environment Electronics

2013 ◽  
Vol 10 (2) ◽  
pp. 80-88 ◽  
Author(s):  
M. Mirgkizoudi ◽  
C. Liu ◽  
P. P. Conway ◽  
S. Riches
Keyword(s):  
Storage Temperature ◽  
Temperature Cycling ◽  
Silicon On Insulator ◽  
Effect Of Temperature ◽  
Electronic Components ◽  
Wire Bond ◽  
Temperature Exposure ◽  
Vibration Tests ◽  
Combined Parameters ◽  
Temperature Storage

The performance of electronics in harsh environments is often affected by a combination of environmental factors. Qualification tests on such electronics are normally carried out by separate environmental tests such as temperature storage, temperature cycling and vibration tests. This approach may miss the effects of combined parameters, where for example, there may be degradation in a vibration environment that may be accelerated by temperature related effects on material properties. This paper presents results from a study of the combined effects of temperature and vibration on wire bonded interconnections that are used in the production of high temperature electronic components. The study is focused on the testing of electronic components under the combination of temperature exposure up to 250°C and vibration loading with a frequency range between 500 Hz and 2,000 Hz and acceleration up to 20 Grms. The study covers aspects of wire bond connections and their failure mechanisms, where the effect of wire loop height and length under separate and combined vibration and temperature tests has been investigated. The study has also assessed the effect on packaged Silicon on Insulator (SOI) devices assembled into ceramic packages under representative combined temperature and vibration profiles. The work has shown that the combined effect of temperature and vibration has increased the susceptibility of wire bond interconnections to vibration-induced failures.

Combined Temperature and Vibration Testing for Wire Bond Interconnections in Harsh Environment Electronics

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000335-000344 ◽  
Author(s):  
M. Mirgkizoudi ◽  
C. Liu ◽  
P. Conway ◽  
S. Riches
Keyword(s):  
Storage Temperature ◽  
Initial Study ◽  
Temperature Cycling ◽  
Silicon On Insulator ◽  
Harsh Environments ◽  
Effect Of Temperature ◽  
Vibration Testing ◽  
Electronic Components ◽  
Wire Bond ◽  
Temperature Exposure

The performance of electronics located in harsh environments is often affected by a combination of environmental factors. Qualification tests on such electronics are normally carried out by separate environmental tests such as temperature storage, temperature cycling and vibration tests. This approach may mask the effects of combined parameters, where degradation in a vibration environment may be accelerated by temperature related effects on material properties, for example. This paper presents details of an initial study into the combined effects of temperature and vibration on wire bonded interconnections used in the production of high temperature electronic components. The study is focused on the testing of electronic components under the combination of temperature exposure up to 250°C and vibration loading with a frequency range between 50Hz and 2000Hz and acceleration up to 20g rms. The study covers the fundamental aspects of wire bond connections and their failure mechanisms, where the effect of wire loop height and length under separate and combined vibration and temperature tests has been investigated. The study has also assessed the effect on packaged silicon on insulator (SOI) devices assembled into ceramic packages under representative combined temperature and vibration profiles. The work has shown that the combined effect of temperature and vibration has increased the susceptibility of wire bond interconnections to vibration induced failures and vibration testing under the applied temperature is recommended for assessment of components for harsh environments.

SPACE THERMAL SIMULATION FOR SATELLITE HEAT TRANSFER DESIGN EVALUATION

1974 ◽  
Author(s):  
Vasily D. Prian ◽  
Andy T. Calimbas ◽  
Edward A. LaBlanc
Keyword(s):  
Heat Transfer ◽  
Thermal Simulation ◽  
Design Evaluation

Intermittent Failures in High Pin Count Packaging

2006 ◽  
Author(s):  
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick
Keyword(s):  
Failure Analysis ◽  
Shape Analysis ◽  
State Of The Art ◽  
Process Variation ◽  
High Reliability ◽  
Temperature Cycling ◽  
Assembly Process ◽  
System Failures ◽  
Industrial Grade ◽  
Corrective Actions

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

Failure Analysis of Short Faults on Advanced Wire-Bond and Flip-Chip Packages with Scanning SQUID Microscopy

2004 ◽  
Author(s):  
Steve K. Hsiung ◽  
Kevan V. Tan ◽  
Andrew J. Komrowski ◽  
Daniel J. D. Sullivan ◽  
Jan Gaudestad
Keyword(s):  
Magnetic Fields ◽  
Integrated Circuits ◽  
Quantum Interference ◽  
Flip Chip ◽  
Infrared Emission ◽  
Fault Analysis ◽  
Wire Bond ◽  
Overlay Design ◽  
Scanning Squid ◽  
Metal Layers

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.

Sign in / Sign up

Export Citation Format

Share Document