TCAD Modeling of Resistive-Switching of HfO2 Memristors: Efficient Device-Circuit Co-Design for Neuromorphic Systems

In neuromorphic computing, memristors (or “memory resistors”) have been primarily studied as key elements in artificial synapse implementations, where the memristor provides a variable weight with intrinsic long-term memory capabilities, based on its modifiable resistive-switching characteristics. Here, we demonstrate an efficient methodology for simulating resistive-switching of HfO2 memristors within Synopsys TCAD Sentaurus—a well established, versatile framework for electronic device simulation, visualization and modeling. Kinetic Monte Carlo is used to model the temporal dynamics of filament formation and rupture wherein additional band-to-trap electronic transitions are included to account for polaronic effects due to strong electron-lattice coupling in HfO2. The conductive filament is modeled as oxygen vacancies which behave as electron traps as opposed to ionized donors, consistent with recent experimental data showing p-type conductivity in HfOx films having high oxygen vacancy concentrations and ab-initio calculations showing the increased thermodynamic stability of neutral and charged oxygen vacancies under conditions of electron injection. Pulsed IV characteristics are obtained by inputting the dynamic state of the system—which consists of oxygen ions, unoccupied oxygen vacancies, and occupied oxygen vacancies at various positions—into Synopsis TCAD Sentaurus for quasi-static simulations. This allows direct visualization of filament electrostatics as well as the implementation of a nonlocal, trap-assisted-tunneling model to estimate current-voltage characteristics during switching. The model utilizes effective masses and work functions of the top and bottom electrodes as additional parameters influencing filament dynamics. Together, this approach can be used to provide valuable device- and circuit-level insight, such as forming voltage, resistance levels and success rates of programming operations, as we demonstrate.

Investigating physical model interface in the TCAD Sentaurus environment

Currently, the application SDevice software package TCAD Sentaurus is a reliable tool for electrophysical simulation of silicon CMOS transistors operating in the temperature range of -60 °C – +125 °C. To adapt the modeling process to specific physical conditions of the devices, application SDevice has an extensive library of models of electrophysical parameters, in particular models of mobility or band gap energy. However, when the device operates under extreme cryogenic conditions, there is a need to rework these models using a special Physical Model Interface (PMI). The paper presents methodological features of work with PMI and results of implementation of custom parameter models for silicon devices.

THE CONDUCTIVITY OF SILICON MESARESISTORS IN JOULE HEATING CONDITIONS

The article presents the results on the influence of geometric factors and surface states at the interfaces on the processes of electronic transport in thin silicon films on dielectric. TCAD Sentaurus calculations of the mesaresistors relative change resistance (ΔR\R) on the applied power, have shown the decisive role of traps with "shallow" states in the film conductivity. Their presence leads to a nonmonotonic dependence ΔR\R.

An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length

Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET). Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.

Simulation of dynamic characteristics of GaN p-i-n avalanche diode operating as particle detector with internal gain

An evolution of the transient characteristics of the GaN p-i-n diodes, operating in the avalanche mode and acting as particle sensors, has been simulated by using the Synopsys TCAD Sentaurus software package and the drift-diffusion approach. Profiling of the charge generation, recombination and drift-diffusion processes has been performed over a nanosecond time-scale with a precision of a few picoseconds and emulated through the photo-excitation of an excess carrier domain at different locations of the active volume of a diode. Shockley–Read–Hall (SRH), Auger and radiative recombination processes have been taken into account. Fast and slow components within a current transient have been analysed based on the consideration of the carrier spatial distribution at different instants of the avalanche process. The internal gain due to charge multiplication ensures the sufficient charge collection on electrodes of the relatively thin (5 µm) diode operating in the avalanche mode. It has been shown that the simulated evolution of the detector transient responses by employing the drift-diffusion approach reproduces properly the qualitative modifications of the main features of a detector with an internal gain, realized by induction of the avalanche processes governed by the applied external voltage.

Study of the side gate junctionless transistor in accumulation region

Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation. Findings We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime. Originality/value The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applications

Recently, thanks to the advancement in SiC process technology, the deep trench termination (DT2) technique becomes an appropriate choice for future high voltage SiC power device. This technique termination is based on the use of a wide and deep trench, which is filled by a dielectric and associated with a field plate. DT2 technique increases the breakdown voltage (VBR) to a value near to the ideal one that can be obtained in a plan case; and at the same time, reduces drastically the chip area comparing to the previous conventional techniques. In this work, the DT2 used for a 3 kV 4H-SiC bipolar vertical diode is presented. Simulations using TCAD SENTAURUS software show that a maximum breakdown voltage of 3286 V at room temperature can be achieved with a deep trench of 20μm corresponding to 98 % of a parallel plane breakdown voltage for the drift layer of 18 μm. Those simulations also point out the important impact of the structure of the trench; the dielectric critical electric filled (Ec), the permittivity (εr) of the dielectric filled, etching defects as microtrench, fixed charges at the interfaces...on the VBR of power device.