Variation Investigation of Junction-less Transistor with Side-wall Charge-plasma Structure Induced by Line Edge Roughness

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict49897.2020.9278349 ◽

2020 ◽

Author(s):

Kai Liu ◽

Hung-Chih Chin ◽

Haijun Lou ◽

Kuan-Chang Chang ◽

Xinnan Lin

Keyword(s):

Side Wall ◽

Plasma Structure ◽

Line Edge Roughness ◽

Charge Plasma ◽

Edge Roughness ◽

Download Full-text

Strain Consideration of Charge Plasma Structure on Junctionless Transistor With Line Edge Roughness

2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) ◽

10.1109/edssc.2018.8487066 ◽

2018 ◽

Author(s):

Wentao Li ◽

Haijun Lou ◽

Xinnan Lin

Keyword(s):

Plasma Structure ◽

Line Edge Roughness ◽

Charge Plasma ◽

Edge Roughness ◽

Junctionless Transistor

Download Full-text

Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect

IEEE Transactions on Electron Devices ◽

10.1109/ted.2018.2812241 ◽

2018 ◽

Vol 65 (5) ◽

pp. 1873-1879 ◽

Author(s):

Wenbo Wan ◽

Haijun Lou ◽

Ying Xiao ◽

Xinnan Lin

Keyword(s):

Line Edge Roughness ◽

Roughness Effect ◽

Charge Plasma ◽

Edge Roughness ◽

Junctionless Transistor

Download Full-text

Characterization of Line-Edge Roughness in Cu/Low-kInterconnect Pattern

Japanese Journal of Applied Physics ◽

10.1143/jjap.47.2501 ◽

2008 ◽

Vol 47 (4) ◽

pp. 2501-2505 ◽

Author(s):

Atsuko Yamaguchi ◽

Daisuke Ryuzaki ◽

Ken-ichi Takeda ◽

Jiro Yamamoto ◽

Hiroki Kawada ◽

...

Keyword(s):

Line Edge Roughness ◽

Download Full-text

Study of the acid-diffusion effect on line edge roughness using the edge roughness evaluation method

Journal of Vacuum Science & Technology B Microelectronics Processing and Phenomena ◽

10.1116/1.1490392 ◽

2002 ◽

Vol 20 (4) ◽

pp. 1342 ◽

Author(s):

Masaki Yoshizawa ◽

Shigeru Moriya

Keyword(s):

Evaluation Method ◽

Line Edge Roughness ◽

Diffusion Effect ◽

Acid Diffusion ◽

Edge Roughness ◽

On Line ◽

Roughness Evaluation

Download Full-text

Interactions Between Line Edge Roughness and Random Dopant Fluctuation in Nonplanar Field-Effect Transistor Variability

IEEE Transactions on Electron Devices ◽

10.1109/ted.2013.2276072 ◽

2013 ◽

Vol 60 (10) ◽

pp. 3277-3284 ◽

Author(s):

Greg Leung ◽

Chi On Chui

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Line Edge Roughness ◽

Random Dopant Fluctuation ◽

Edge Roughness ◽

Effect Transistor ◽

Download Full-text

Application of cellular neural networks in the measurement of line-width and line edge roughness

10.1117/12.676727 ◽

2006 ◽

Author(s):

Hong-bo Li ◽

Xue-zheng Zhao ◽

Wei Chu ◽

Ning Li

Keyword(s):

Neural Networks ◽

Cellular Neural Networks ◽

Line Edge Roughness ◽

Download Full-text

Fabrication of low line edge roughness mold by SOG replica method

Digest of Papers. 2004 International Microprocesses and Nanotechnology Conference, 2004. ◽

10.1109/imnc.2004.245725 ◽

2004 ◽

Author(s):

Y. Kurashima ◽

H. Hiroshima ◽

M. Komuro ◽

N. Yamazaki ◽

J. Taniguchi ◽

...

Keyword(s):

Replica Method ◽

Line Edge Roughness ◽

Download Full-text

A new physical model and experimental measurements of copper interconnect resistivity considering size effects and line-edge roughness (LER)

2009 IEEE International Interconnect Technology Conference ◽

10.1109/iitc.2009.5090396 ◽

2009 ◽

Author(s):

Gerald Lopez ◽

Jeffrey Davis ◽

James Meindl

Keyword(s):

Physical Model ◽

Size Effects ◽

Experimental Measurements ◽

Line Edge Roughness ◽

Copper Interconnect ◽

Download Full-text

Estimation of critical dimension and line edge roughness using a neural network

Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena ◽

10.1116/6.0000806 ◽

2021 ◽

Vol 39 (3) ◽

pp. 032602

Author(s):

Dehua Li ◽

Soo-Young Lee ◽

Jin Choi ◽

Seom-Beom Kim ◽

Chan-Uk Jeon

Keyword(s):

Neural Network ◽

Critical Dimension ◽

Line Edge Roughness ◽

Download Full-text

Novel wafer-scale uniform layer-by-layer etching technology for line edge roughness reduction and surface flattening of 3D Ge channels

2015 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm.2015.7409703 ◽

2015 ◽

Author(s):

Y. Morita ◽

T. Maeda ◽

H. Ota ◽

W. Mizubayashi ◽

S. O'uchi ◽

...

Keyword(s):

Layer By Layer ◽

Line Edge Roughness ◽

Surface Flattening ◽

Wafer Scale ◽

Uniform Layer ◽

Download Full-text