A 3GHz low power, MOS varactor voltage controlled oscillator for implantable ultra wideband applications in CMOS Silicon-On-Sapphire (SOS) process

2013 ◽  
Author(s):  
Ayobami Iji ◽  
Xie Zhu ◽  
Michael Heimlich
Keyword(s):  
Low Power ◽  
Ultra Wideband ◽  
Voltage Controlled Oscillator ◽  
Mos Varactor

A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control

2018 ◽  
Vol 27 (10) ◽  
pp. 1850160 ◽  
Author(s):  
Manoj Kumar ◽  
Dileep Dwivedi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Supply Voltage ◽  
Back Gate ◽  
Tuning Method ◽  
Low Power Cmos ◽  
Improved Performance ◽  
Mos Varactor

This paper presents a new design of low power voltage controlled oscillator (VCO) circuit using three transistors NOR-gate and I-MOS (inversion mode) varactor tuning method. Variation in the oscillation frequency has been obtained by varying the output load capacitance with the use of I-MOS varactor tuning consisting of two PMOS transistors connected in parallel. Variable capacitance across the I-MOS varactor has been achieved by varying the source/drain voltage ([Formula: see text] and back-gate voltage ([Formula: see text]. Variation of [Formula: see text] from 1[Formula: see text]V to 2[Formula: see text]V provides the frequency deviation from 1.970[Formula: see text]GHz to 1.379[Formula: see text]GHz with I-MOS width of 8 [Formula: see text]m at power supply voltage ([Formula: see text] of 1.8[Formula: see text]V. Power consumption of the circuit is 1.296[Formula: see text]mW with [Formula: see text] of 1.8[Formula: see text]V. The results have been obtained for different I-MOS varactor widths like 5[Formula: see text][Formula: see text]m, 8[Formula: see text][Formula: see text]m and 10[Formula: see text][Formula: see text]m. Further, variations in the frequency have been obtained from 0.650 GHz to 2.584 GHz with the Vdd variation from 1[Formula: see text]V to 3[Formula: see text]V. In addition, by variations of [Formula: see text] from 0[Formula: see text]V to 1.8[Formula: see text]V and [Formula: see text] from 1[Formula: see text]V to 3[Formula: see text]V, the proposed oscillators operate in the frequency range from 0.556[Formula: see text]GHz to 2.584[Formula: see text]GHz for 8[Formula: see text][Formula: see text]m width of I-MOS varactor. Proposed VCO circuit show a phase noise of [Formula: see text][Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset from the carrier frequency and the figure of merit (FoM) for the VCO is 154.51[Formula: see text]dB/Hz. Proposed VCO shows an improved performance in terms of power consumption, output frequency and FoM.

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

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