A low overhead high speed histogram based test methodology for analog circuits and IP cores

2005 ◽  
Author(s):  
S. Bahukudumbi ◽  
K. Bharath
Keyword(s):  
Analog Circuits ◽  
High Speed ◽  
Test Methodology ◽  
Ip Cores

scholarly journals High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz Mir
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
High Efficiency ◽  
Critical Path ◽  
Fir Filters ◽  
Path Delay ◽  
Look Up Table ◽  
Improved Performance ◽  
Ip Cores ◽  
Low Efficiency

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources.

scholarly journals AC_ICAP: A Flexible High Speed ICAP Controller

2015 ◽  
Vol 2015 ◽  
pp. 1-15 ◽  
Author(s):  
Luis Andres Cardona ◽  
Carles Ferrer
Keyword(s):  
High Speed ◽  
Access Port ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Speed Up ◽  
Run Time ◽  
Ip Cores ◽  
Similar Solutions ◽  
Internal Configuration ◽  
Run Time Reconfiguration

The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

scholarly journals Experimental Investigation of Spur Gear Efficiency

2007 ◽  
Author(s):  
T. T. Petry-Johnson ◽  
A. Kahraman ◽  
N. E. Anderson ◽  
D. R. Chase
Keyword(s):  
Surface Roughness ◽  
High Speed ◽  
Mechanical Load ◽  
Spur Gear ◽  
Total Power ◽  
Test Machine ◽  
Gear Mesh ◽  
Test Methodology ◽  
Gear Efficiency ◽  
Accuracy And Repeatability

In this study, a test methodology was developed for measurement of spur gear efficiency under high-speed and variable torque conditions. A power-circulating test machine was designed to operate at speeds to 10,000 rpm and transmitted power levels to 700 kW. A precision torque measurement system was implemented and its accuracy and repeatability in measuring torque loss in the power loop was demonstrated. Tests were conducted on gears with two values of module, and two surface roughness levels, operating in a dry sump jet-lubrication environment with three different gear lubricants. These tests were used to quantify the influence of these parameters on load-dependent (mechanical), load-independent (spin), and total power loss. Trends in mechanical gear mesh efficiency and total gearbox efficiency were discussed in terms of rotational speed and transmitted torque. Finally, recommendations were made for the design of spur gear pairs, surface roughness, and lubricant selection for improved efficiency.

A 10-Bit Column-Parallel Single Slope ADC Based on Two-Step TDC with Error Calibration for CMOS Image Sensors

2015 ◽  
Vol 24 (04) ◽  
pp. 1550054 ◽  
Author(s):  
Jiangtao Xu ◽  
Jing Yu ◽  
Fujun Huang ◽  
Kaiming Nie
Keyword(s):  
Analog Circuits ◽  
High Speed ◽  
Propagation Delay ◽  
Image Sensors ◽  
Time Interval ◽  
Cmos Process ◽  
Digital Converter ◽  
Cmos Image Sensors ◽  
Time Problem ◽  
The Impact

This paper presents a 10-bit column-parallel single slope analog-to-digital converter (SS ADC) with a two-step time-to-digital converter (TDC) to overcome the long conversion time problem in conventional SS ADC for high-speed CMOS image sensors (CIS). The time interval proportional to the input signal is generated by a ramp generator and a comparator, which is digitized by a two-step TDC consisting of coarse and fine conversions to achieve a high-precision time-interval measurement. To mitigate the impact of propagation delay mismatch, a calibration circuit is also proposed to calibrate the delay skew within -T/2 to T/2. The proposed ADC is designed in 0.18 μm CMOS process. The power dissipation of each column circuit is 232 μW at supply voltages of 3.3 V for the analog circuits and 1.8 V for the digital blocks. The post simulation results indicate that the ADC achieves a SNDR of 60.89 dB (9.82 ENOB) and a SFDR of 79.98 dB at a conversion rate of 2 MS/s after calibration, while the SNDR and SFDR are limited to 41.52 dB and 67.64 dB, respectively before calibration. The differential nonlinearity (DNL) and integral nonlinearity (INL) without calibration are +15.80/-15.29 LSB and +1.68/-15.34 LSB while they are reduced down to +0.75/-0.25 LSB and +0.76/-0.78 LSB with the proposed calibration.

A PC-Based Synchronous Controller for NC Gear Grinding Machines Using Multithread CBN Wheel

1999 ◽  
Vol 123 (4) ◽  
pp. 590-597 ◽  
Author(s):  
T. Emura ◽  
L. Wang ◽  
M. Yamanaka ◽  
H. Nakamura ◽  
Y. Kato ◽  
...  
Keyword(s):  
Analog Circuits ◽  
High Speed ◽  
Production Costs ◽  
Two Phase ◽  
Pitch Accuracy ◽  
High Productivity ◽  
Cbn Wheel ◽  
Gear Grinding ◽  
Phase Type ◽  
Grinding Machines

This paper describes a synchronous controller for high-productivity NC gear grinding machines that use a screw-shaped CBN wheel of multithread. The authors developed a high-precision controller for productive-type NC gear grinding machines in 1995. Because it was based on analog circuits, it required very complex electrical circuits. In this paper, we propose a PC-based synchronous controller to decrease production costs and add useful functions to it. The most useful one added this time is a function to increase pitch accuracy of gear ground with the multithread CBN wheel. Next useful one is a function to attain high-accuracy initial meshing between gear and CBN wheel. Because grinding-spindle and work spindle rotate at a high-speed, two-phase type PLL is applied to the controller. Grinding experiments showed that the newly developed controller has excellent performance.

scholarly journals Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Oscar Montiel-Ross ◽  
Jorge Quiñones ◽  
Roberto Sepúlveda
Keyword(s):  
Parallel Programming ◽  
High Speed ◽  
High Performance ◽  
Hardware Description Language ◽  
System Response ◽  
Description Language ◽  
Tuning Method ◽  
Hardware Description ◽  
Ip Cores ◽  
Fuzzy Pd

This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

scholarly journals Swift Reliability Test Methodology of 100G High-Speed, Energy-efficient Electro-Absorption Modulated Lasers (EML) for Green Datacenter Networks

2016 ◽  
Vol 3 (1) ◽  
pp. 74 ◽  
Author(s):  
Jack Jia-Sheng Huang ◽  
Yu-Heng Jan ◽  
Jesse Chang ◽  
Yi-Ching Hsu ◽  
Dawei Ren ◽  
...  
Keyword(s):  
Optical Networks ◽  
Energy Efficient ◽  
High Speed ◽  
Data Communication ◽  
Field Performance ◽  
Information Storage ◽  
Reliability Test ◽  
Data Traffic ◽  
Gigabit Ethernet ◽  
Test Methodology

High-speed transceivers are receiving great interest due to the demand for huge data traffic and information storage capacities in the Big Data era. Recently, 100 Gigabit Ethernet (100GbE) has become an IEEE standardized data communication protocol. The 100G quad small form-factor pluggable (QSFP) transceiver is one of the key technological enablers in the high-speed optical networks. In this paper, we study the reliability current dependence for the four-lambda QSFP (4x25G) EML devices that are employed in the 100G QSFP transceivers. In order to meet the energy-efficient and environmental requirements, we develop a swift reliability test methodology that can provide fast, accurate reliability assessment to ensure robust long-term field performance. We discuss the acceleration factor and extrapolation for the energy-efficient reliability test.

scholarly journals Effect of CNTs Parameter Variation on the Performance of Analog Device

2020 ◽  
Vol 9 (4) ◽  
pp. 237-241
Keyword(s):  
Analog Circuits ◽  
Power Dissipation ◽  
High Speed ◽  
Ballistic Transport ◽  
Average Power ◽  
Systems Design ◽  
Parameter Variation ◽  
Charge Carriers ◽  
Analog Device ◽  
Current Carrying Capability

Carbon nanotubes (CNTs) have emerged as a prominent material for present day nano-scale systems design. In spite of their widespread use in biology, and nano-electro mechanical systems (NEMS, CNTs have encroached upon conventional MOSFETs for the design of low power and high speed circuits. Because CNT possesses higher current carrying capability, higher transconductance and near ballistic transport of charge carriers. The diameter of the CNTs laid from the Source to the Drain in a CNFET has the significant influence on the characteristics of the device itself as well as on the features of circuits implemented using the said CNFET. Such variations in circuit parameters with CNT diameter can be shown to be more pronounced in analog circuits as compared to digital CNFET-based designs. The present work attempts to investigate the effect of diameter variation on a versatile analog building block (ABB) viz. the inverting current conveyor. It is demonstrated that various parameters of the ICC-II under scrutiny, like voltage bandwidth, current bandwidth, average power dissipation, etc. depend on the diameter of CNT(s) used in the CNFETs. HSPICE simulations performed on a 0.9V; 32nm CNFET-based ICC-II are included to exemplify the dependencies studied.

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