A novel stacked class-E-like power amplifier with dual drain output power technique in 0.18 um RFSOI CMOS technology

2018 ◽  
Author(s):  
Jiangchuan Ren ◽  
Ruofan Dai ◽  
Jun He ◽  
Jun Xiao ◽  
Weiran Kong ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Cmos Technology ◽  
Class E

scholarly journals Analysis and Compensation of the AM-AM and AM-PM Distortion for CMOS Cascode Class-E Power Amplifier

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Wen An Tsou ◽  
Wen Shen Wuen ◽  
Tzu Yi Yang ◽  
Kuei Ann Wen
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Source ◽  
Nonlinear Capacitance ◽  
Power Added Efficiency ◽  
Equivalent Impedance ◽  
Common Gate ◽  
Class E

Analysis and compensation methodology of the AM-AM and AM-PM distortion of cascode class-E power amplifiers are presented. A physical-based model is proposed to illustrate that the nonlinear capacitance and transconductance cause the AM-AM and AM-PM distortion when modulating the supply voltage of the PA. A novel methodology that can reduce the distortion is also proposed. By degenerating common-gate transistor into a resistor, the constant equivalent impedance is obtained so that the AM-AM and AM-PM distortion is compensated. An experimental prototype of 2.6 GHz cascode class-E power amplifier with the AM-AM and AM-PM compensation has been integrated in a 0.18 μm CMOS technology, occupies a total die area of 1.6 mm2. It achieves a drain efficiency of 17.8% and a power-added efficiency of 16.6% while delivering 12 dBm of linear output power and drawing 31 mA from a 1.8 V supply. Finally, a co-simulation result demonstrated that, when the distortion of the PA has been compensated, the EVM is improved from −17 dB to −19 dB with an IEEE802.11a-like signal source.

scholarly journals Efficiency Analysis of Low Power Class-E Power Amplifier

2014 ◽  
Vol 8 (5) ◽  
pp. 19
Author(s):  
Mousa Yousefi ◽  
Ziaadin Daie Koozehkanani ◽  
Jafar Sobhi ◽  
Hamid Jangi ◽  
Nasser Nasirezadeh
Keyword(s):  
Low Power ◽  
Output Power ◽  
Power Amplifier ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Efficiency Analysis ◽  
Simulation Results ◽  
On Chip ◽  
Power Class ◽  
Class E

This paper presents an analysis of effect of inductor and switch losses on output power and efficiency of low power class-E power amplifier. This structure is suitable for integrated circuit implementation. Since on chip inductors have large losses than the other elements, the effect of their losses on efficiency has been investigated. Equations for the efficiency have been derived and plotted versus the value of inductors and switch losses. Derived equations are evaluated using MATLAB. Also, Cadence Spectre has been used for schematic simulation. Results show a fair matching between simulated power loss and efficiency and MATLAB evaluations. Considering the analysis, the proposed power amplifier shows about 13 % improvement in power effiency at 400 MHz and -2 dBm output power. It is simulated in 0.18 ?m CMOS technology.

Design methodology for a switching-mode RF CMOS power amplifier with an output transformer

2015 ◽  
Vol 8 (3) ◽  
pp. 471-477
Author(s):  
Changhyun Lee ◽  
Changkun Park
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Design Methodology ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Rf Cmos ◽  
Power Transistor ◽  
Voltage Output ◽  
Switching Mode ◽  
Output Transformer

In this study, we propose a design methodology for a switching-mode RF CMOS power amplifier with an output transformer. For a given supply voltage, output power, and target efficiency, the initial values of the transistor size, output inductance, and capacitance can be sequentially determined during the design of the power amplifier. The breakdown voltage of the power transistor is considered in the design methodology. To prove the feasibility of the proposed design methodology, we provide the design example of a 2.4-GHz switching-mode CMOS power amplifier with 180-nm RF CMOS technology. From the measured results, the feasibility of the proposed design methodology is proved.

scholarly journals A Modified Design of Class-E Power Amplifier with Balanced FETs and High Output Power for RFID Applications

2021 ◽  
Vol 19 ◽  
pp. 28-37
Author(s):  
Muhammad Noaman Zahid ◽  
Jianliang Jiang ◽  
Heng Lu ◽  
Hengli Zhang
Keyword(s):  
Radio Frequency ◽  
Output Power ◽  
Power Amplifier ◽  
Radio Frequency Identification ◽  
Field Effect Transistors ◽  
High Output Power ◽  
Matching Network ◽  
Power Added Efficiency ◽  
High Output ◽  
Class E

In Radio Frequency (RF) communication, a Power Amplifier (PA) is used to amplify the signal at the required power level with less utilization of Direct Current (DC) power. The main characteristic of class-E PA is sturdy nonlinearity due to the switching mode action. In this study, a modified design of class-E PA with balanced Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and high output power for Electronic Article Surveillance (EAS) Radio Frequency Identification (RFID) application is presented. MOSFETs are adjusted to have high output performance of about 80% for RFID-based EAS system. A matching network is also proposed for accurate matching because there are differences in the behavior between RF waves and low frequency waves. The design of a matching network is a tradeoff among the complexity, adjustability, implementation, and bandwidth for the required output power and frequency. The implemented PA is capable of providing 44.8 dBm output power with Power-Added Efficiency (PAE) of 78.5% at 7.7 MHz to 8.7 MHz.

scholarly journals A 65nm CMOS 60 GHz Class F-E Power Amplifier for WPAN Applications

2013 ◽  
Vol 8 (1) ◽  
pp. 7-13
Author(s):  
N. Deltimple ◽  
S. Dréan ◽  
E. Kerhervé ◽  
B. Martineau ◽  
D. Belot
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Cost ◽  
Cmos Technology ◽  
Area Network ◽  
60 Ghz ◽  
Power Stage ◽  
Lumped Elements ◽  
Class E ◽  
Class F

This work presents a two-stage 60 GHz Power Amplifier designed in a 65nm CMOS technology dedicated to low cost Wireless Personal Area Network (WPAN) applications. In order to provide a high efficiency operation, the PA is based on a Class E power stage. A Class F driver stage is also designed to provide a square waveform signal to the Class-E power stage. To realize the output networks of both driver and power stage at 60 GHz, distributed elements are used instead of lumped elements. The post-layout simulation results show a saturated output power of 15 dBm with a peak PAE of 26% at 60 GHz. It achieves a gain of 15dB at 60 GHz.

A 2.4-GHz 0.18μm Full-CMOS Single-Stage Class-E Power Amplifier With Temperature Effect for ISM Band Wireless Communication

2007 ◽  
Author(s):  
Mu-Chun Wang ◽  
Zhen-Ying Hsieh ◽  
Chieu-Ying Hsu ◽  
Shuang-Yuan Chen ◽  
Heng-Sheng Huang
Keyword(s):  
Temperature Effect ◽  
Output Power ◽  
Power Amplifier ◽  
Single Stage ◽  
Design System ◽  
Cmos Process ◽  
Power Added Efficiency ◽  
Ism Band ◽  
Stage Class ◽  
Class E

In this paper, we present a single-stage class-E power amplifier with multiple-gated shape as well as 0.18μm complementary metal-oxide-semiconductor (CMOS) process for 2.4GHz Industry-Science-Medicine (ISM) band. This power amplifier is able to be easily integrated into the system-on-chip (SoC) circuit. For the competition of lower cost and high integration in marketing concern, CMOS technology is fundamentally better than GaAs technology. We adopt the Advanced Design System software in circuit simulation coming from Agilent Company through the Chip Implementation Center (CIC) channel plus TSMC 0.18 μm device models. The simulation results with temperature effect, show the good performance such as an output power achievement of +22dBm under a 1.8V supply voltage; the power-added efficiency (PAE) is over 30%; the output impedance (S22) and the input impedance (S11) are fully lower than −15dB; the power gain (S21) is +11dB; the inverse isolation (S12) is below −26dB. This amplifier reaches its 1-dB compression point at an output level of 16.5dBm related to the input power 6.5dBm position. The output power with temperature variation from 0°C to 125°C depicts an acceptable spec. range, too.

EFFICIENT DATA AND POWER TRANSFER FOR BIO-IMPLANTED DEVICES BASED ON ASK MODULATION TECHNIQUES

2012 ◽  
Vol 12 (05) ◽  
pp. 1240030 ◽  
Author(s):  
SAAD MUTASHAR ◽  
M. A. HANNAN ◽  
SALINA A. SAMAD ◽  
AINI HUSSAIN
Keyword(s):  
Power Amplifier ◽  
Power Efficiency ◽  
Data Transfer ◽  
Software Tool ◽  
Cmos Technology ◽  
Integrated System ◽  
Band Frequency ◽  
Modulation Techniques ◽  
Implanted Devices ◽  
Class E

This paper presents a fully integrated system for implanted micro-system devices with efficient power and data transfer based on amplitude shift keying (ASK) modulation techniques. A proposed efficient class-E power amplifier is presented. The design presents a full transcutaneous inductive powering system to transfer power and data from an outside human body to implanted devices such as implanted microsystems to stimulate and monitor the nerves and muscles with low band frequency of 13.56 MHz according to the industrial–scientific–medical (ISM) band to avoid the tissue damage. A novel ASK demodulator powered with 1.9 V is proposed with a power recovery system. The modulation index is 13% and the modulation rate 7.3% with data rate 1 Mbit/s, and with power efficiency 66%. The system has been designed using 0.35-μm fabricated CMOS technology. The mathematical model is given and the design is simulated using OrCAD PSpice 16.2 software tool and for real-time simulation, the electronic workbench MULISIM 11 has been used to simulate the class-E power amplifier.

A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS

2011 ◽  
Vol 3 (2) ◽  
pp. 99-105 ◽  
Author(s):  
Dixian Zhao ◽  
Ying He ◽  
Lianming Li ◽  
Dieter Joos ◽  
Wim Philibert ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Peak Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
60 Ghz ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Saturated Output Power

A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.

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