Design methodology for a switching-mode RF CMOS power amplifier with an output transformer

2015 ◽  
Vol 8 (3) ◽  
pp. 471-477
Author(s):  
Changhyun Lee ◽  
Changkun Park
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Design Methodology ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Rf Cmos ◽  
Power Transistor ◽  
Voltage Output ◽  
Switching Mode ◽  
Output Transformer

In this study, we propose a design methodology for a switching-mode RF CMOS power amplifier with an output transformer. For a given supply voltage, output power, and target efficiency, the initial values of the transistor size, output inductance, and capacitance can be sequentially determined during the design of the power amplifier. The breakdown voltage of the power transistor is considered in the design methodology. To prove the feasibility of the proposed design methodology, we provide the design example of a 2.4-GHz switching-mode CMOS power amplifier with 180-nm RF CMOS technology. From the measured results, the feasibility of the proposed design methodology is proved.

scholarly journals Analysis and Compensation of the AM-AM and AM-PM Distortion for CMOS Cascode Class-E Power Amplifier

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Wen An Tsou ◽  
Wen Shen Wuen ◽  
Tzu Yi Yang ◽  
Kuei Ann Wen
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Source ◽  
Nonlinear Capacitance ◽  
Power Added Efficiency ◽  
Equivalent Impedance ◽  
Common Gate ◽  
Class E

Analysis and compensation methodology of the AM-AM and AM-PM distortion of cascode class-E power amplifiers are presented. A physical-based model is proposed to illustrate that the nonlinear capacitance and transconductance cause the AM-AM and AM-PM distortion when modulating the supply voltage of the PA. A novel methodology that can reduce the distortion is also proposed. By degenerating common-gate transistor into a resistor, the constant equivalent impedance is obtained so that the AM-AM and AM-PM distortion is compensated. An experimental prototype of 2.6 GHz cascode class-E power amplifier with the AM-AM and AM-PM compensation has been integrated in a 0.18 μm CMOS technology, occupies a total die area of 1.6 mm2. It achieves a drain efficiency of 17.8% and a power-added efficiency of 16.6% while delivering 12 dBm of linear output power and drawing 31 mA from a 1.8 V supply. Finally, a co-simulation result demonstrated that, when the distortion of the PA has been compensated, the EVM is improved from −17 dB to −19 dB with an IEEE802.11a-like signal source.

Numerical Analysis of the Supply Voltage of a Switching Mode RF CMOS Power Amplifier to Enhance Its Efficiency

2013 ◽  
Vol 55 (10) ◽  
pp. 2479-2484 ◽  
Author(s):  
Hoyong Hwang ◽  
Donghwan Seo ◽  
Changhyun Lee ◽  
Changkun Park
Keyword(s):  
Numerical Analysis ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Rf Cmos ◽  
Switching Mode

Investigation of the power transistor size related to the efficiency of switching-mode RF CMOS power amplifier

2013 ◽  
Vol 56 (1) ◽  
pp. 110-117 ◽  
Author(s):  
Hoyong Hwang ◽  
Donghwan Seo ◽  
Jonghoon Park ◽  
Changkun Park
Keyword(s):  
Power Amplifier ◽  
Rf Cmos ◽  
Power Transistor ◽  
Switching Mode

scholarly journals K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 890
Author(s):  
Kyu-Jin Choi ◽  
Jae-Hyun Park ◽  
Seong-Kyun Kim ◽  
Byung-Sung Kim
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Output Resistance ◽  
Power Added Efficiency ◽  
High Output ◽  
K Band

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

scholarly journals Broadband push-pull power amplifier design methodology based on the GaN component base for high-performance nonlinear junction detectors

2019 ◽  
Vol 30 ◽  
pp. 01011
Author(s):  
Vladimir Klokov ◽  
Nikolay Kargin ◽  
Alexander Garmash ◽  
Ekaterina Guzniaeva
Keyword(s):  
Theoretical Model ◽  
Output Power ◽  
Power Amplifier ◽  
High Performance ◽  
Design Methodology ◽  
Wide Band ◽  
Signal Power ◽  
Large Signal ◽  
Amplifier Design ◽  
Gain Characteristic

The paper presents a description of design methodology for wide-band push-pull large-signal power amplifier based on GaN transistor with an output power of more than 10 W for high-performance Nonlinear Junction Detectors, which allows achieving optimal convergence of the theoretical model in practice, as well as increasing the efficiency of the power amplifier while maintaining a linear gain characteristic.

A 60GHz power amplifier using 90-nm RF-CMOS technology

2011 ◽  
Author(s):  
Nan Zhang ◽  
Lingling Sun ◽  
Jincai Wen ◽  
Jun Liu ◽  
Jia Lou ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Cmos Technology ◽  
Rf Cmos

Design Method of Class-F Power Amplifier With Output Power of $-$ 20 dBm and Efficient Dual Supply Voltage Transmitter

2014 ◽  
Vol 61 (10) ◽  
pp. 2978-2986 ◽  
Author(s):  
Shunta Iguchi ◽  
Akira Saito ◽  
Kazunori Watanabe ◽  
Takayasu Sakurai ◽  
Makoto Takamiya
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Design Method ◽  
Class F

A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Chang-Hsi Wu ◽  
Hong-Cheng You ◽  
Shun-Zhao Huang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Power Efficiency ◽  
Supply Voltage ◽  
Maximum Output Power ◽  
Dual Band ◽  
Maximum Output ◽  
Power Combiner ◽  
Power Added Efficiency ◽  
Chip Size

Abstract An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m2, the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of −9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm2.

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