Removing W Polymer Residue from BEOL Structures Using DSP+ (Dilute Sulfuric-Peroxide-HF) Mixture – A Case Study

2012 ◽  
Vol 195 ◽  
pp. 128-131 ◽  
Author(s):  
Hun Hee Lee ◽  
Min Sang Yun ◽  
Hyun Wook Lee ◽  
Jin Goo Park
Keyword(s):  
High Speed ◽  
Semiconductor Device ◽  
Environmental Issues ◽  
Low Power Consumption ◽  
Device Performance ◽  
Metal Gate ◽  
Feature Size ◽  
High K ◽  
Removal Of Metal

As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+(dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+chemicals for cleaning processes also increases [.

Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme

2009 ◽  
Vol 145-146 ◽  
pp. 207-210 ◽  
Author(s):  
Farid Sebaai ◽  
Jose Ignacio Del Agua Borniquel ◽  
Rita Vos ◽  
Philippe Absil ◽  
Thomas Chiarella ◽  
...  
Keyword(s):  
Integration Scheme ◽  
Device Performance ◽  
New Materials ◽  
Metal Gate ◽  
Speed Increase ◽  
Poly Silicon ◽  
High K ◽  
Consumption Reduction ◽  
High K Materials ◽  
Scaling Features

With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].

scholarly journals Analyzing Mega City-Regions through Integrating Urbanization and Eco-Environment Systems: A Case Study of the Beijing-Tianjin-Hebei Region

2019 ◽  
Vol 16 (1) ◽  
pp. 114 ◽  
Author(s):  
Li Tian ◽  
Gaofeng Xu ◽  
Chenjing Fan ◽  
Yue Zhang ◽  
Chaolin Gu ◽  
...  
Keyword(s):  
High Speed ◽  
Environmental Issues ◽  
Ecological Systems ◽  
Groundwater Depletion ◽  
Rapid Urbanization ◽  
City Regions ◽  
External Forces ◽  
Internal And External Factors ◽  
Casual Relationship

The high-speed economic growth of mega city-regions in China has been characterized by rapid urbanization accompanied by a series of environmental issues ranging from widespread soil contamination to groundwater depletion. This article begins with an analysis of the interaction between urbanization and the ecological system and reviews existing frameworks for analyzing urban and ecological systems. By taking the Beijing-Tianjin-Hebei region as an example, the article introduces a conceptual framework to analyze mega city-regions and forecast possible interactions between urbanization and eco-environment by applying simulation model. The proposed framework and its components can provide guidance to identify the impacts of urbanization and external forces such as globalization on eco-environment by integrating the internal and external factors, synthesize the complex components of mega city-regions in databases, understand and diagnose the casual relationship between urban policies and ecological consequences.

Work around Moore’s Law: Current and next Generation Technologies

2011 ◽  
Vol 110-116 ◽  
pp. 3278-3283
Author(s):  
Khaled Salah Mohamed
Keyword(s):  
High Performance ◽  
Quantum Computer ◽  
Optical Wireless ◽  
Metal Gate ◽  
Feature Size ◽  
Strained Si ◽  
High K ◽  
Cmos Transistor ◽  
Beyond Cmos ◽  
Technology Level

Interconnect dimensions and CMOS transistor feature size approach their physical limits, therefore scaling will no longer play an important role in performance improvement. So, instead of trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a heterogeneous system that is high performance will be introduced “moore than more” and CMOS replacement”beyond CMOS” will be explored. This paper focuses on Technology level trends where it presents “More Moore”:New Architectures (SOI, FinFET, Twin-Well),”More Moore” :New Materials (High-K, Metal Gate, Strained-Si) ,”More than Moore”:New Interconnects Schemes (3D, NoC, Optical, Wireless), and ”Beyond CMOS” :New Devices (Molecular Computer, Biological computer, Quantum Computer) .

Materials and Process Integration Issues in Metal Gate/High-k Stacks and Their Dependence on Device Performance

2019 ◽  
Vol 11 (4) ◽  
pp. 265-274 ◽  
Author(s):  
Alessandro Callegari ◽  
Katherina Babich ◽  
Sufi Zafar ◽  
Vijay Narayanan ◽  
Takashi Ando ◽  
...  
Keyword(s):  
Process Integration ◽  
Device Performance ◽  
Metal Gate ◽  
High K

Physical origin of dipole formation at high-k/SiO2 interface in metal-oxide-semiconductor device with high-k/metal gate structure

2010 ◽  
Vol 96 (15) ◽  
pp. 152907 ◽  
Author(s):  
Xiaolei Wang ◽  
Kai Han ◽  
Wenwu Wang ◽  
Shijie Chen ◽  
Xueli Ma ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Semiconductor Device ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Physical Origin ◽  
Metal Gate ◽  
Gate Structure ◽  
High K

Material Loss Impact on Device Performance for 32nm CMOS and Beyond

2009 ◽  
Vol 145-146 ◽  
pp. 245-248 ◽  
Author(s):  
Brian K. Kirkpatrick ◽  
James J. Chambers ◽  
Steven L. Prins ◽  
Deborah J. Riley ◽  
Wei Ze Xiong ◽  
...  
Keyword(s):  
Process Control ◽  
Device Performance ◽  
Semiconductor Technology ◽  
New Materials ◽  
Metal Gate ◽  
Material Loss ◽  
Front End ◽  
High K ◽  
Physical Features

As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.

High K / Metal Gate of Short-Channel SOI NMOSFET Research

2011 ◽  
Vol 383-390 ◽  
pp. 6902-6907
Author(s):  
Gang Lu ◽  
Bo Zhao
Keyword(s):  
Electrical Properties ◽  
Theoretical Analysis ◽  
Leakage Current ◽  
Device Performance ◽  
Gate Leakage Current ◽  
Metal Gate ◽  
Short Channel ◽  
Gate Structure ◽  
High K ◽  
Simulation Results

Short-channel under TaCN/La2O3gate structure SOI NMOSFET has been studied in this paper, contrast with the traditional gate structure gate leakage current and others electrical properties, using TaCN/La2O3gate structure，significantly improved short-channel device performance etc. Additionally, the gate structure in the L=40nm, 30nm and 20nm of C-V characteristic and output characteristic are also studied; all the simulation results coincide with the theoretical analysis.

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