A 16 Bit 250MSPS Pipeline ADC

2014 ◽  
Vol 602-605 ◽  
pp. 2744-2747
Author(s):  
Ting Li ◽  
Yong Zhang ◽  
Yan Wang ◽  
Lu Liu ◽  
Xu Wang
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Pipeline Adc ◽  
Front End ◽  
Sampling Network ◽  
Sinusoidal Input ◽  
High Efficient ◽  
Circuit Structure

In this paper, a 16 bit 250MSPS pipelined ADC is presented. To alleviate noise induced by mismatching of the MDAC sampling network and comparator sampling network, scaling network structure is applied; to implement high-speed sampling, a high-efficient front-end circuit structure is presented; to further improve the sampling rate, a double duty cycle clock circuit is presented; to improve the linearity of the ADC, the sample and hold circuit is removed and the improved clock controlled boost circuit is used. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 0.18um CMOS process.

scholarly journals A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 199 ◽  
Author(s):  
Peiyuan Wan ◽  
Limei Su ◽  
Hongda Zhang ◽  
Zhijie Chen
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Sampling Rate ◽  
Measured Signal ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Sinusoidal Input ◽  
Bit Flip

An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.

scholarly journals A Codesigned Integrated Photonic Electronic Neuron

2021 ◽  
Author(s):  
Lorenzo De Marinis ◽  
Alessandro Catania ◽  
Piero Castoldi ◽  
Giampiero Contestabile ◽  
Paolo Bruschi ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Activation Function ◽  
Memory Storage ◽  
Cmos Process ◽  
Analog To Digital ◽  
Analog Electronics ◽  
Front End ◽  
Execution Speed ◽  
Electronic Neuron

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage. In this paper we introduce a precision-scalable integrated photonic-electronic multiply-accumulate neuron, namely PEMAN. The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device, based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front end, has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed with resolution and power consumption, it outperforms its analog electronics counterparts both in terms of speed and power consumption, and brings substantial improvements also compared to a leading GPU.

scholarly journals CMOS Receiver Front-End Architecture for High-Speed SI-POF Links

1970 ◽  
pp. 10
Author(s):  
C. Gimeno ◽  
C. Aldea ◽  
S. Celma ◽  
F. Aznar
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Large Diameter ◽  
Input Resistance ◽  
Cmos Process ◽  
Large Area ◽  
Silicon Photodiode ◽  
Limited Bandwidth ◽  
Flipped Voltage Follower ◽  
Front End

This works presents a new CMOS analog front-end for short-reach high-speed optical communications which compensates the limited bandwidth of POF channels and is suitable for the required large area photodetectorf The proposed pseudo-differential architecture, formed by a preamplifier and an equalizer, has been designed in a standard 0.18-μm CMOS process with a 1-V supply voltage targeting gigabit transmission for NRZ modulation. The preamplifier is based on the flipped voltage follower stage to attain a very low input resistance in order to handle the large phodiode capacitance (3 pF). The equalizer can adjust the high-frequency boosting and the gain, to compensate for the variation of the characteristics of the channel due to length of the fiber, connections, etc. causing subtantial changes of the fiber bandwidth. Reliable electrical models are employed for a Mitsubishi GH SI-POF with 10-m to 50-m length and for a S5972 silicon photodiode from Hamamatsu suitable for such a fiber due to its large diameter (0.8 mm) and responsivity at 650 nm (0.44A/W). The bandwidth of the received signal can be enhanced from 100 MHz to 1.4 GHz and from 300 MHz to 1.4 GHz for a 50-m and 10-m POF respectively. The proposed circuit shows a transimpedance of 41.5 dBΩ while the theoretical sensitivity from noise performance is below -7.5 dBm with a BER = 10-12. The power consumption is below 16 mW from 1-V supply voltage. In conclusion it targets 1.25 Gbps through a 1-mm SI-POF up to 50-m length with a commercial Si PIN photodiode.

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC

2013 ◽  
Author(s):  
Ting Li ◽  
Dongbing Fu ◽  
Yong Zhang ◽  
Yan Wang ◽  
Lu Liu ◽  
...  
Keyword(s):  
High Speed ◽  
Pipelined Adc ◽  
Front End

A LOW-VOLTAGE LOW-POWER 10-BIT 200 MS/S PIPELINED ADC IN 90 NM CMOS

2010 ◽  
Vol 19 (02) ◽  
pp. 393-405 ◽  
Author(s):  
SAHEL ABDINIA ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Pipeline Adc ◽  
Class A ◽  
Reduction Techniques ◽  
Dynamic Comparators

This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-VP-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage.

scholarly journals Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2545
Author(s):  
Kihyun Kim ◽  
Sein Oh ◽  
Hyungil Chae
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Process ◽  
Noise Shaping ◽  
Mismatch Error ◽  
Analog To Digital ◽  
Current Sharing ◽  
High Sampling Rate ◽  
Good Energy ◽  
Two Phases

A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.

A High Speed Open-Loop Track/Hold Circuit in CMOS Process

2013 ◽  
Vol 756-759 ◽  
pp. 4302-4305
Author(s):  
Zheng Ping Zhang ◽  
Yong Lu Wang ◽  
Ming Liu
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Open Loop ◽  
Cmos Process ◽  
High Sampling ◽  
High Sampling Rate ◽  
Interleaved Structure ◽  
Offset Compensation ◽  
Loop Track

A high speed open-loop track/hold circuit in 0.18um CMOS process is presented. Open-loop and differential architecture are adopted to obtain high bandwidth and high speed;time-interleaved structure is used to reach a high sampling rate;source negative feedback and offset compensation are used to improve the linearity of the circuit.Simulation results show that with 396.875MHz input, 1.6GSPS sampling rate, driving the pre-amplifier of ADC, the thack/hold circuits SFDR(spurious-free dynamic range) is 75.8dB,satisfying the demand of 12 bits ADC.The circuit features high sampling rate,wide bandwidth,high SFDR and universal.

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