Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs

2010 ◽  
Author(s):  
Davide Marano ◽  
Gaetano Palumbo ◽  
Salvatore Pennisi
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Analytical Figure Of Merit

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

Design Trade-offs for Low-power and High Figure-of-merit LNA

2006 ◽  
Author(s):  
Hsien-ku Chen ◽  
J. R. Sha ◽  
Da-chiang Chang ◽  
Ying-zong Juang ◽  
Chin-fong Chiu
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Trade Offs ◽  
High Figure

scholarly journals High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

2021 ◽  
Author(s):  
Prashant Kumar ◽  
Munish Vashishath ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Analytical Model ◽  
Threshold Voltage ◽  
Figure Of Merit ◽  
Double Gate ◽  
Short Channel ◽  
Ultra Low Power ◽  
High K ◽  
Channel Effects ◽  
High K Dielectric

Abstract This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29% improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

Design of Low Voltage Low Power ADC for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 561-566
Author(s):  
Si Kui Ren ◽  
Zhi Qun Li
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Chip Area ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm2. It results in a figure-of-merit (FOM) of 0.11pJ/step.

A CAPACITIVE MEMs VERILOGA-BASED SENSOR SYSTEM FOR BUILDING INTEGRITY MONITORING

2011 ◽  
Vol 08 (02) ◽  
pp. 153-159 ◽  
Author(s):  
JUAN SANTANA ◽  
RICHARD VAN DEN HOVEN
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
Signal To Noise Ratio ◽  
Strain Sensors ◽  
Excitation Voltage ◽  
Motion Artefacts ◽  
Signal To Noise ◽  
Ultra Low Power ◽  
Residual Motion ◽  
Capacitive Mems

A capacitive MEMS Ultra-Low-Power readout for accelerometers and strain sensors using VerilogA models is presented. The VerilogA model of the accelerometers and strain sensors allows the simulation of a system in a half-bridge configuration. The gain of the system is controlled by integrating pulses from the excitation voltage which accurately controls the Signal-to-Noise ratio. A Figure-of-Merit of [Formula: see text] was achieved for a sensor range of ±2.0 g and ±20,000 με over a 100 Hz bandwidth. Residual motion artefacts are also canceled by the system.

Design tradeoff for SiGe 0.35-μm BiCMOS low-power and high figure-of-merit LNA

2005 ◽  
Vol 47 (1) ◽  
pp. 65-68 ◽  
Author(s):  
Hsien-Ku Chen ◽  
Hsien-Jui Chen ◽  
Ying-Zong Juang ◽  
Chin-Fong Chiu
Keyword(s):  
Low Power ◽  
Figure Of Merit ◽  
High Figure
Sign in / Sign up

Export Citation Format

Share Document