Low-power, low-offset stacked analog latch using an offset cancellation technique

2011 ◽  
Author(s):  
Minehiko Tateno ◽  
Hiroki Date ◽  
Kenichi Ohhata
Keyword(s):  
Low Power ◽  
Offset Cancellation ◽  
Low Offset

An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC

2014 ◽  
Vol 598 ◽  
pp. 365-370
Author(s):  
Shuo Zhang ◽  
Zong Min Wang ◽  
Liang Zhou
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Cmos Process ◽  
Total Current ◽  
Flash Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Current Consumption ◽  
Low Offset

This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1:2 dutyratio. The improved comparator is implemented in 0.35μm CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with σ = 2.0347mV,and total current consumption is 17.59μA, while the offset voltage and total current consumption of the primary one is -5.649mV with σ = 14.254mV and 57.18μA respectively.

A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC

2013 ◽  
Vol 22 (07) ◽  
pp. 1350061 ◽  
Author(s):  
ZHANGMING ZHU ◽  
WEITIE WANG ◽  
YUHENG GUAN ◽  
SHUBIN LIU ◽  
YU XIAO ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Low Power ◽  
High Speed ◽  
Cmos Process ◽  
Amplifier Circuit ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Low Offset

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

A novel online offset-cancellation mechanism in a low-power 6-bit 2GS/s flash-ADC

2018 ◽  
Vol 99 (2) ◽  
pp. 219-229 ◽  
Author(s):  
Abdollah Amini ◽  
Ali Baradaranrezaeii ◽  
Mina Hassanzadazar
Keyword(s):  
Low Power ◽  
Flash Adc ◽  
Offset Cancellation

scholarly journals A low-power dynamic comparator for low-offset applications

Integration ◽  
2019 ◽  
Vol 69 ◽  
pp. 23-30 ◽  
Author(s):  
Ata Khorami ◽  
Roghayeh Saeidi ◽  
Manoj Sachdev ◽  
Mohammad Sharifkhani
Keyword(s):  
Low Power ◽  
Dynamic Comparator ◽  
Power Dynamic ◽  
Low Offset

A novel low offset low power CMOS dynamic comparator

2018 ◽  
Vol 96 (1) ◽  
pp. 147-158 ◽  
Author(s):  
Priyesh P. Gandhi ◽  
N. M. Devashrayee
Keyword(s):  
Low Power ◽  
Dynamic Comparator ◽  
Low Power Cmos ◽  
Low Offset
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