A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC
2013 ◽
Vol 22
(07)
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pp. 1350061
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A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.
2013 ◽
Vol 22
(04)
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pp. 1350018
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2014 ◽
Vol 598
◽
pp. 365-370
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2017 ◽
Vol 26
(07)
◽
pp. 1750115
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2015 ◽
Vol 85
(1)
◽
pp. 181-192
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2019 ◽
Vol 8
(3)
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pp. 5966-5970
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2005 ◽
Vol 15
(02)
◽
pp. 459-476
2020 ◽
Vol 9
(12)
◽
pp. 323-328
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