Damping-factor-control frequency compensation technique for low-voltage low-power large capacitive load applications

2003 ◽  
Author(s):  
A.K.N. Leung ◽  
P.K.T. Mok ◽  
Wing Hung Ki ◽  
J.K.O. Sin
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Damping Factor ◽  
Frequency Compensation ◽  
Control Frequency ◽  
Capacitive Load ◽  
Compensation Technique

Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

2000 ◽  
Vol 35 (2) ◽  
pp. 221-230 ◽  
Author(s):  
Ka Nang Leung ◽  
P.K.T. Mok ◽  
Wing-Hung Ki ◽  
J.K.O. Sin
Keyword(s):  
Damping Factor ◽  
Frequency Compensation ◽  
Control Frequency ◽  
Capacitive Load

Frequency-Compensated Bulk-Driven TIA Suitable for Low-Voltage Low-Power Applications

2020 ◽  
pp. 2150121
Author(s):  
Urvashi Bansal ◽  
Maneesha Gupta ◽  
Niranjan Raj
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Transimpedance Amplifier ◽  
Frequency Compensation ◽  
Suitable Alternative ◽  
Small Signal Analysis ◽  
Cmos Design ◽  
Spiral Inductors ◽  
Compensation Technique ◽  
Good Agreement

The importance of a transimpedance amplifier in an optical transceiver is very well known. In this paper, a novel CMOS design of the bulk-driven transimpedance amplifier (BD-TIA) is given where the bridge-shunt peaking-based frequency compensation technique is exploited to improve frequency response. A pre-existing active inductor has been used for the same. The electrical characteristics and functioning of this inductor simulator make it a suitable alternative to both floating and grounded spiral inductors. In order to verify the workability of the proposed circuit, it has been simulated with TSMC CMOS 0.18[Formula: see text][Formula: see text]m process parameters. The proposed circuit is useful in low-voltage low-power VLSI applications as it uses a single supply of 0.75[Formula: see text]V. The power consumption of BD-TIA is very low, being 0.37[Formula: see text]mW, because a standard MOSFET has been replaced by a bulk-driven MOSFET (BDMOS), while the 3-dB bandwidth is observed to be 4.5[Formula: see text]GHz. The mathematical investigation and small signal analysis show that the simulation results are in good agreement.

scholarly journals CAPACITOR-LESS LOW-DROPOUT VOLTAGE REGULATOR

2014 ◽  
pp. 50-55
Author(s):  
SRIRANGANATHA SAGAR.K.N ◽  
POORNIMA N. ◽  
VIJAYA KUMAR. V
Keyword(s):  
Output Voltage ◽  
Total Error ◽  
Cmos Technology ◽  
Damping Factor ◽  
Frequency Compensation ◽  
Load Variations ◽  
Power Supply Rejection Ratio ◽  
Control Frequency ◽  
Low Dropout Regulator ◽  
On Chip

A 1.2-V 40-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitorfree operation. The proposed LDO has been implemented in a tsmc65nm CMOS technology, and the total error of the output voltage due to line and load variations is less. Moreover, the output voltage can recover with ≈2.3μs for full load current changes. The power-supply rejection ratio at 1 MHz is 26 dB.

Design and Simulation of Low-Power Multistage Amplifiers

2011 ◽  
Vol 378-379 ◽  
pp. 655-658
Author(s):  
Ming Yuan Ren
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Frequency Compensation ◽  
Transient Responses ◽  
Gain Bandwidth ◽  
Silicon Area ◽  
Multistage Amplifiers ◽  
Capacitive Load ◽  
The Stability ◽  
Multistage Amplifier

This paper presents a low-power multistage amplifier with a novel capacitor-multiplier frequency compensation (CMFC) technique. The proposed compensation strategy can allow the circuit to occupy less silicon area and to drive large capacitive loads more effectively. Moreover, smaller physical capacitance results in higher gain-bandwidth product (GBW) and improved transient responses. Furthermore, the capacitor multiplier stage (CMS) embedded in CMFC creates a left-half plane (LHP) zero, which boosts the phase margin and enhances the stability of the amplifier. Implemented in a commercial 0.5-μm CMOS technology and driving 500pF capacitive load, a three-stage CMFC amplifier achieves over 120dB gain, 1.699MHz GBW and 1.625V/μS average slew rate, while only dissipating 330μW under 3.3V supply.

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