scholarly journals Flip-Chip Integration of InP to SiN Photonic Integrated Circuits

2020 ◽  
Vol 38 (9) ◽  
pp. 2630-2636 ◽  
Author(s):  
Michael Theurer ◽  
Martin Moehrle ◽  
Ariane Sigmund ◽  
Karl-Otto Velthaus ◽  
Ruud M. Oldenbeuving ◽  
...  
2015 ◽  
Vol 2015 (1) ◽  
pp. 000616-000620 ◽  
Author(s):  
S. Bernabé ◽  
G. Pares ◽  
B. Blampey ◽  
K. Rida ◽  
O. Castany ◽  
...  

Achieving high data speed (typically Nx25 Gbps) compact optoelectronic modules is now made possible by using Photonic Integrated Circuits (PIC) combined with CMOS electronic drivers. Among the techniques that can be used to combine both circuits, flip-chip assembly based on micro-bumps shows several advantages, for example low RF parasitics and high density compared to wire bonding. Using this technique, it is possible to build low consumption photonic receivers working at 25 Gbps.


Author(s):  
R.K. Jain ◽  
T. Malik ◽  
T.R. Lundquist ◽  
Q.S. Wang ◽  
R. Schlangen ◽  
...  

Abstract Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.


Author(s):  
Steve K. Hsiung ◽  
Kevan V. Tan ◽  
Andrew J. Komrowski ◽  
Daniel J. D. Sullivan ◽  
Jan Gaudestad

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.


Author(s):  
Olivier Crépel ◽  
Philippe Descamps ◽  
Patrick Poirier ◽  
Romain Desplats ◽  
Philippe Perdu ◽  
...  

Abstract Magnetic field based techniques have shown great capabilities for investigation of current flows in integrated circuits (ICs). After reviewing the performances of SQUID, GMR (hard disk head technologies) and MTJ existing sensors, we will present results obtained on various case studies. This comparison will show the benefit of each approach according to each case study (packaged devices, flip-chip circuits, …). Finally we will discuss on the obtained results to classify current techniques, optimal domain of applications and advantages.


Author(s):  
Kevin Luke ◽  
Prashanta Kharel ◽  
Christian Reimer ◽  
Lingyan He ◽  
Marko Loncar ◽  
...  

ACS Photonics ◽  
2021 ◽  
Author(s):  
Chen Shang ◽  
Yating Wan ◽  
Jennifer Selvidge ◽  
Eamonn Hughes ◽  
Robert Herrick ◽  
...  

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