Latent open defect detection using phase-sensitive nonlinearity detection technqiue

Microelectronics Reliability ◽

10.1016/0026-2714(96)84402-7 ◽

1996 ◽

Vol 36 (4) ◽

pp. 539

Keyword(s):

Defect Detection ◽

Phase Sensitive ◽

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Latent open defect detection using phase-sensitive nonlinearity detection technique

IEEE Transactions on Components Packaging and Manufacturing Technology Part B ◽

10.1109/96.386274 ◽

1995 ◽

Vol 18 (2) ◽

pp. 358-365 ◽

Author(s):

A. Halperin ◽

T.H. DiStefano ◽

Shinwu Chiang

Keyword(s):

Defect Detection ◽

Detection Technique ◽

Phase Sensitive ◽

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On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory

2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS) ◽

10.1109/lascas51355.2021.9459175 ◽

2021 ◽

Author(s):

Sheetal Barekar ◽

Madan Mali

Keyword(s):

Defect Detection ◽

Detection Technique ◽

Cache Memory ◽

Test Time ◽

Chip Area ◽

Open Defect ◽

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CMOS open defect detection by supply current test

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 ◽

10.1109/date.2001.915071 ◽

2002 ◽

Author(s):

M. Hashizume ◽

M. Ichimiya ◽

H. Yotsuyanagi ◽

T. Tamesada

Keyword(s):

Defect Detection ◽

Current Test ◽

Open Defect ◽

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A new methodology for realistic open defect detection probability evaluation under process variations

29th VLSI Test Symposium ◽

10.1109/vts.2011.5783781 ◽

2011 ◽

Author(s):

Jesus Moreno ◽

Victor Champac ◽

Michel Renovell

Keyword(s):

Defect Detection ◽

Detection Probability ◽

Process Variations ◽

Probability Evaluation ◽

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BICS-based March test for resistive-open defect detection in SRAMs

2010 11th Latin American Test Workshop ◽

10.1109/latw.2010.5550342 ◽

2010 ◽

Author(s):

R. Chipana ◽

L. Bolzani ◽

F. Vargas

Keyword(s):

Defect Detection ◽

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Open Defect Detection of Through Silicon Vias for Structural Power Integrity Test of 3D-ICs

2019 IEEE 23rd Workshop on Signal and Power Integrity (SPI) ◽

10.1109/sapiw.2019.8781656 ◽

2019 ◽

Author(s):

Koutaro Hachiya ◽

Atshushi Kurokawa

Keyword(s):

Defect Detection ◽

Power Integrity ◽

Integrity Test ◽

Structural Power ◽

Through Silicon Vias ◽

3D Ics ◽

Open Defect ◽

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CMOS open defect detection based on supply current in time-variable electric field and supply voltage application

Proceedings 10th Asian Test Symposium ◽

10.1109/ats.2001.990269 ◽

2002 ◽

Author(s):

M. Hashizume ◽

M. Ichimiya ◽

H. Yotsuyanagi ◽

T. Tamesada

Keyword(s):

Electric Field ◽

Defect Detection ◽

Supply Voltage ◽

Time Variable ◽

Variable Electric Field ◽

Voltage Application ◽

Open Defect ◽

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New test methodology for resistive open defect detection in memory address decoders

22nd IEEE VLSI Test Symposium, 2004. Proceedings. ◽

10.1109/vtest.2004.1299235 ◽

2004 ◽

Author(s):

M. Azimane ◽

A.K. Majhi

Keyword(s):

Defect Detection ◽

Test Methodology ◽

Memory Address ◽

Open Defect ◽

Address Decoders

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Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs

2017 IEEE 26th Asian Test Symposium (ATS) ◽

10.1109/ats.2017.53 ◽

2017 ◽

Author(s):

Ayumu Kambara ◽

Hiroyuki Yotsuyanagi ◽

Daichi Miyoshi ◽

Masaki Hashizume ◽

Shyue-Kung Lu

Keyword(s):

Defect Detection ◽

Appearance Time ◽

Test Circuit ◽

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Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards

IEEE Transactions on Components Packaging and Manufacturing Technology ◽

10.1109/tcpmt.2020.2973182 ◽

2020 ◽

Vol 10 (5) ◽

pp. 895-907

Author(s):

Michiya Kanda ◽

Masaki Hashizume ◽

Fara Ashikin Binti ALI ◽

Hiroyuki Yotsuyanagi ◽

Shyue-Kung Lu

Keyword(s):

Defect Detection ◽

Boundary Scan ◽

Circuit Boards ◽

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