Channel-Length Dependence of Low-Field Mobility in Silicon-Nanowire FETs

2009 ◽  
Vol 30 (11) ◽  
pp. 1212-1214 ◽  
Author(s):  
S. Poli ◽  
M.G. Pala
2011 ◽  
Vol 99 (23) ◽  
pp. 233509 ◽  
Author(s):  
Bart Sorée ◽  
Wim Magnus ◽  
William Vandenberghe

2008 ◽  
Vol 1080 ◽  
Author(s):  
Hironori Yoshioka ◽  
Yuichiro Nanen ◽  
Jun Suda ◽  
Tsunenobu Kimoto

ABSTRACTThe n-type silicon nanowire MOSFETs with a nanowire shape being triangular or trapezoidal, have been fabricated on SOI substrates and characterized. The height and bottom-width of the triangular nanowire has been 10 nm and 19 nm, respectively. The devices have shown good gate control, such as a nearly ideal subthreshold slope of 63 mV/decade, high Ion/Ioff ratio of 107, and small drain-induced barrier lowering of 5 mV/V at room temperature. The low field mobility of triangular nanowire has been estimated to be 130 cm2/V·s and shown no difference with the change of the nanowire shape and direction within the investigated range.


VLSI Design ◽  
2001 ◽  
Vol 13 (1-4) ◽  
pp. 163-167 ◽  
Author(s):  
F. M. Bufler ◽  
P. D. Yoder ◽  
W. Fichtner

The strain-dependence of electron transport in bulk Si and deep-submicron MOSFETs is investigated by full-band Monte Carlo simulation. On the bulk level, the drift velocity at medium field strengths is still enhanced above Ge-contents of 20% in the substrate, where the low-field mobility is already saturated, while the saturation velocity remains unchanged under strain. In an n-MOSFET with a metallurgical channel length of 50nm, the saturation drain current is enhanced by up to 11%, but this maximum improvement is essentially already achieved at a Ge-content of 20% emphasizing the role of the low-field mobility as a key indicator of device performance in the deep-submicron regime.


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