Dynamic Gate Stress Induced Threshold Voltage Drift of Silicon Carbide MOSFET

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

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Reliability and Ruggedness of Planar Silicon Carbide MOSFETs

Materials Science Forum ◽

10.4028/www.scientific.net/msf.963.782 ◽

2019 ◽

Vol 963 ◽

pp. 782-787

Author(s):

Kevin Matocha ◽

In Hwan Ji ◽

Sauvik Chowdhury

Keyword(s):

Silicon Carbide ◽

Threshold Voltage ◽

Dielectric Breakdown ◽

Gate Oxide ◽

Time Dependent ◽

Gate Bias ◽

Constant Voltage ◽

Time Dependent Dielectric Breakdown ◽

Planar Silicon ◽

State Of Art

The reliability and ruggedness of Monolith/Littelfuse planar SiC MOSFETs have been evaluated using constant voltage time-dependent dielectric breakdown for gate oxide wearout predictions, showing estimated > 100 year life at VGS=+25V and T=175C. Using extended time high-temperature gate bias, we have shown < 250 mV threshold voltage shifts for > 5000 hours under VGS=+25V and negligible threshold voltage shifts for > 2500 hours under VGS=-10V, both at T=175C. Under unclamped inductive switching, these 1200V, 80 mOhm SiC MOSFETs survive 1000 mJ of avalanche energy, meeting state-of-art ruggedness for 1200V SiC MOSFETs.

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Investigation of the threshold voltage drift in enhancement mode GaN MOSFET under negative gate bias stress

Japanese Journal of Applied Physics ◽

10.7567/jjap.54.044101 ◽

2015 ◽

Vol 54 (4) ◽

pp. 044101 ◽

Cited By ~ 16

Author(s):

Fei Sang ◽

Maojun Wang ◽

Chuan Zhang ◽

Ming Tao ◽

Bing Xie ◽

...

Keyword(s):

Threshold Voltage ◽

Gate Bias ◽

Bias Stress ◽

Enhancement Mode ◽

Voltage Drift ◽

Gate Bias Stress

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Multi-stack insulator to minimise threshold voltage drift in ZnO FET sensors operating in ionic solutions

Micro and Nano Engineering ◽

10.1016/j.mne.2020.100072 ◽

2020 ◽

Vol 9 ◽

pp. 100072

Author(s):

J.D. Akrofi ◽

M. Ebert ◽

J.D. Reynolds ◽

K. Sun ◽

R. Hu ◽

...

Keyword(s):

Threshold Voltage ◽

Ionic Solutions ◽

Voltage Drift

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The Impact of Interfacial Charge Trapping on the Reproducibility of Measurements of Silicon Carbide MOSFET Device Parameters

Crystals ◽

10.3390/cryst10121143 ◽

2020 ◽

Vol 10 (12) ◽

pp. 1143

Author(s):

Maximilian W. Feil ◽

Andreas Huerner ◽

Katja Puschkarsky ◽

Christian Schleich ◽

Thomas Aichinger ◽

...

Keyword(s):

Silicon Carbide ◽

Threshold Voltage ◽

Thermal Conductance ◽

Charge Trapping ◽

Wide Band ◽

Breakdown Field ◽

Parameter Determination ◽

Device Parameter ◽

Measurement Delay ◽

The Impact

Silicon carbide is an emerging material in the field of wide band gap semiconductor devices. Due to its high critical breakdown field and high thermal conductance, silicon carbide MOSFET devices are predestined for high-power applications. The concentration of defects with short capture and emission time constants is higher than in silicon technologies by orders of magnitude which introduces threshold voltage dynamics in the volt regime even on very short time scales. Measurements are heavily affected by timing of readouts and the applied gate voltage before and during the measurement. As a consequence, device parameter determination is not as reproducible as in the case of silicon technologies. Consequent challenges for engineers and researchers to measure device parameters have to be evaluated. In this study, we show how the threshold voltage of planar and trench silicon carbide MOSFET devices of several manufacturers react on short gate pulses of different lengths and voltages and how they influence the outcome of application-relevant pulsed current-voltage characteristics. Measurements are performed via a feedback loop allowing in-situ tracking of the threshold voltage with a measurement delay time of only 1 μs. Device preconditioning, recently suggested to enable reproducible BTI measurements, is investigated in the context of device parameter determination by varying the voltage and the length of the preconditioning pulse.

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