UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI

2003 ◽  
Author(s):  
Kyu-won Choi ◽  
A. Chatterjee
Keyword(s):  
Low Power ◽  
Power Optimization ◽  
Ultra Low Power ◽  
Low Power Cmos ◽  
Cmos Vlsi

An ultra-low-power CMOS voltage reference generator based on body bias technique

2013 ◽  
Vol 44 (12) ◽  
pp. 1145-1153 ◽  
Author(s):  
Yanhan Zeng ◽  
Yirong Huang ◽  
Yunling Luo ◽  
Hong-Zhou Tan
Keyword(s):  
Low Power ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Reference Generator ◽  
Low Power Cmos ◽  
Cmos Voltage Reference ◽  
Body Bias

scholarly journals Ultra-Low Power CMOS Readout for Resonant MEMS Strain Sensors

Proceedings ◽  
2018 ◽  
Vol 2 (13) ◽  
pp. 973
Author(s):  
Marco Crescentini ◽  
Cinzia Tamburini ◽  
Luca Belsito ◽  
Aldo Romani ◽  
Alberto Roncaglia ◽  
...  
Keyword(s):  
Low Power ◽  
Power Supply ◽  
First Generation ◽  
Negative Resistance ◽  
Low Noise ◽  
Strain Sensors ◽  
Current Conveyors ◽  
Ultra Low Power ◽  
Active Elements ◽  
Low Power Cmos

This paper presents an ultra-low power, silicon-integrated readout for resonant MEMS strain sensors. The analogue readout implements a negative-resistance amplifier based on first-generation current conveyors (CCI) that, thanks to the reduced number of active elements, targets both low-power and low-noise. A prototype of the circuit was implemented in a 0.18-µm technology occupying less than 0.4 mm2 and consuming only 9 µA from the 1.8-V power supply. The prototype was earliest tested by connecting it to a resonant MEMS strain resonator.

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

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