An ultra low-voltage, ultra low-power CMOS mixer using the body effect

In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[Formula: see text]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [Formula: see text]-V supply voltage with the sample rate of 140[Formula: see text]MS/s show SFDR [Formula: see text] 64.37[Formula: see text]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.

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The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology

Advances in Computer and Electrical Engineering - Design and Modeling of Low Power VLSI Systems ◽

10.4018/978-1-5225-0190-9.ch009 ◽

2016 ◽

pp. 229-251

Author(s):

Kavyashree P. ◽

Siva S. Yellampalli

Keyword(s):

Low Power ◽

Low Voltage ◽

Noise Figure ◽

Supply Voltage ◽

Cmos Technology ◽

Ultra Low Power ◽

Low Voltage Operation ◽

Common Gate ◽

Low Power Cmos ◽

Power Application

In this chapter, an ultra low power CMOS Common Gate LNA (CGLNA) with a Capacitive Cross-Coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the Noise Figure (NF) and power dissipation. In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCC-CGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.

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An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2007.902216 ◽

2007 ◽

Vol 54 (10) ◽

pp. 843-847 ◽

Cited By ~ 114

Author(s):

LuÍs H. C. Ferreira ◽

Tales Cleber Pimenta ◽

Robson L. Moreno

Keyword(s):

Low Power ◽

Low Voltage ◽

Input Output ◽

Ultra Low Power ◽

Rail To Rail ◽

Low Power Cmos ◽

Output Swing

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An Efficient Architecture for Accurate and Low Power CMOS Analog Multiplier

Journal of Circuits System and Computers ◽

10.1142/s0218126621500456 ◽

2020 ◽

pp. 2150045

Author(s):

Tohid aghaei ◽

Ali Naderi Saatlo

Keyword(s):

Low Power ◽

Power Dissipation ◽

Harmonic Distortion ◽

Cmos Technology ◽

The Body ◽

Body Effect ◽

Low Power Dissipation ◽

Low Power Cmos ◽

Amplitude Modulator ◽

Four Quadrant

A new analog four-quadrant multiplier in CMOS technology is proposed using translinear loops (TLs). The novelty of the work includes an improved structure resulting in high precision output, low power consumption and low body effect error. The higher accuracy is achieved using a symmetrical arrangement of the proposed multiplier, where the errors on the two sides of circuit are subtracted from each other. The simple structure, as well as the sharing bias branch in the squaring circuits, leads to the low power dissipation of the multiplier circuit. In addition, the proposed circuit is thoroughly analyzed in terms of the body effect error and the results are presented. In order to validate the performance of the circuit, the designed multiplier is used in two useful applications: frequency doubler and amplitude modulator. The post layout simulation results of the circuit are performed using Cadence Virtuoso and HSPICE with level 49 parameters (BSIM3v3) of TSMC 0.18[Formula: see text][Formula: see text]m technology. The results show a nonlinearity of 0.93%, a total harmonic distortion (THD) of 0.98% at a frequency of 1[Formula: see text]MHz, a [Formula: see text]3[Formula: see text]dB bandwidth of 736[Formula: see text]MHz and a maximum power dissipation of 0.0619[Formula: see text]mW.

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Ultra low-voltage ultra low-power CMOS threshold voltage reference

Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06 ◽

10.1145/1150343.1150368 ◽

2006 ◽

Cited By ~ 1

Author(s):

Luis H. C. Ferreira ◽

Tales C Pimenta ◽

Robson L. Moreno ◽

Wilhelmus A. V. Noije

Keyword(s):

Low Power ◽

Threshold Voltage ◽

Low Voltage ◽

Voltage Reference ◽

Ultra Low Power ◽

Low Power Cmos

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A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11020019 ◽

2021 ◽

Vol 11 (2) ◽

pp. 19

Author(s):

Francesco Centurelli ◽

Riccardo Della Sala ◽

Pietro Monsurrò ◽

Giuseppe Scotti ◽

Alessandro Trifiletti

Keyword(s):

Low Power ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Process ◽

Slew Rate ◽

Large Signal ◽

Output Stage ◽

Ultra Low Power ◽

Input Stage ◽

Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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