Bonding Position Accuracy of Direct Transfer Bonding, Chip-on-wafer Bonding for III-V/Si Heterogeneous Integration

Author(s):  
Hiromu Onodera ◽  
Takehiko Kikuchi ◽  
Yoshitaka Ohiso ◽  
Tomohiro Amemiya ◽  
Nobuhiko Nishiyama
2014 ◽  
Vol 783-786 ◽  
pp. 2028-2033
Author(s):  
Mitsuru Takenaka ◽  
Shinichi Takagi

Heterogeneous integration of III-V compound semiconductors and Ge on the Si platform is one of the promising technologies for enhancing the performance of metal-oxide-semiconductor field effect transistors (MOSFETs) beyond the 10-nm technology node because of their high carrier mobilities. In addition, the III-Vs and Ge are also promising materials for photonic devices. Thus, we have investigated III-V/Ge device engineering for CMOS photonics, enabling monolithic integration of high-performance III-V/Ge CMOS transistors and III-V/Ge photonics on Si. The direct wafer bonding of III-V on Si has been investigated to form III-V on Insulator for III-V CMOS photonics. Extremely-thin-body InGaAs MOSFETs with the gate length of approximately 55 nm have successfully been demonstrated by using the wafer bonding. InP-based photonic-wire waveguide devices including micro bends, arrayed waveguide gratings, grating couplers, optical switches, and InGaAs photodetectors have also been demonstrated on the III-V-OI wafer. The gate stack formation on Ge is one of the critical issues for Ge MOSFETs. Recently, we have successfully demonstrated high-quality GeOx/Ge MOS interfaces formed by thermal oxidation and plasma oxidation. High-performance Ge pMOSFET and nMOSFET with thin EOT have been obtained using the GeOx/Ge MOS interfaces. We have also demonstrated that GeOx surface passivation is effective to reduce the dark current of Ge photodetectors in conjunction with gas-phase doped junction. We have also investigated strained SiGe optical modulators. We expect that compressive strain in SiGe enhances modulation efficiency, and an extremely small VπL of 0.033 V-cm is predicted. III-V/Ge heterogeneous integration is one of the promising ways for achieving ultrahigh performance electronic-photonic integrated circuits.


Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 339 ◽  
Author(s):  
Boyan Huang ◽  
Chenxi Wang ◽  
Hui Fang ◽  
Shicheng Zhou ◽  
Tadatomo Suga

High-precision aligned wafer bonding is essential to heterogeneous integration, with the device dimension reduced continuously. To get the alignment more accurately and conveniently, we propose a moiré-based alignment method using centrosymmetric grating marks. This method enables both coarse and fine alignment steps without requiring additional conventional cross-and-box alignment marks. Combined with an aligned wafer bonding system, alignment accuracy better than 300 nm (3σ) was achieved after bonding. Furthermore, the working principle of the moiré-based alignment for the backside alignment system was proposed to overcome the difficulty in bonding of opaque wafers. We believe this higher alignment accuracy is feasible to satisfy more demanding requirements in wafer-level stacking technologies.


2015 ◽  
Vol 2015 (1) ◽  
pp. 000621-000626 ◽  
Author(s):  
Colin McDonough ◽  
Doug La Tulipe ◽  
Dan Pascual ◽  
Paul Tariello ◽  
John Mucci ◽  
...  

A fully functional Si photonics and 65-nm CMOS heterogeneous 3D integration is demonstrated for the first time in a 300mm production environment. Direct oxide wafer bonding was developed to eliminate voids between SOI photonics and bulk Si CMOS wafers. A via-last, Cu through-oxide via (TOV) 3D integration was developed for low capacitance electrical connections with no impact on CMOS performance. 3D yield approaching 100% was demonstrated on >20,000 via chains.


2013 ◽  
Vol 50 (9) ◽  
pp. 1055-1061 ◽  
Author(s):  
H.- S. Lee ◽  
Z. Li ◽  
M. Sun ◽  
K. Ryu ◽  
T. Palacios

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