scholarly journals Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

2020 ◽  
Vol 15 (1) ◽  
Author(s):  
Ruibo Chen ◽  
Hongxia Liu ◽  
Wenqiang Song ◽  
Feibo Du ◽  
Hao Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Triggering Mechanism ◽  
Esd Protection ◽  
Tcad Simulation ◽  
P Type ◽  
28 Nm ◽  
Latch Up

Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

A Digital-Based Ultra-Low-Voltage Pseudo-Differential CMOS Schmitt Trigger

2019 ◽  
Vol 29 (04) ◽  
pp. 2020002
Author(s):  
Yasin Bastan ◽  
Parviz Amiri
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Design Procedure ◽  
Schmitt Trigger ◽  
Input Voltage ◽  
Cmos Process ◽  
Differential Mode ◽  
Digital Cmos ◽  
Hysteresis Width ◽  
Chip Area

A digital-based Pseudo-differential Schmitt trigger is proposed in this paper which is suitable for ultra-low voltages and pure digital integrated circuit technologies. The proposed Schmitt trigger is implemented according to the design procedure of an analog Schmitt trigger and only using digital CMOS inverters. It is composed of a differential comparator consisting of two CMOS inverters and a cross-coupled inverter pair positive feedback which has simultaneously two outputs of noninverting and inverting. The proposed circuit is the only digital Schmitt trigger which operates in differential mode and its hysteresis center can be changed by the input voltage. Implementing the circuit in digital-based allows the proposed Schmitt trigger to operate in 0.4[Formula: see text]V ultra-low-voltage. Principle operation of the proposed circuit is discussed theoretically and using formulas and its performance is verified by simulation in TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. The proposed circuit occupies only [Formula: see text][Formula: see text][Formula: see text]m2 chip area due to the very low number of transistors. The hysteresis width of the proposed Schmitt trigger is 205[Formula: see text]mV and consumes only 6.64[Formula: see text]nW power.

Ultracompact ESD Protection With BIMOS-Merged Dual Back-to-Back SCR in Hybrid Bulk 28-nm FD-SOI Advanced CMOS Technology

2017 ◽  
Vol 64 (10) ◽  
pp. 3991-3997 ◽  
Author(s):  
Philippe Galy ◽  
Johan Bourgeat ◽  
Nicolas Guitard ◽  
Jean-Daniel Lise ◽  
David Marin-Cudraz ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Esd Protection ◽  
28 Nm

scholarly journals Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 445
Author(s):  
Hou ◽  
Du ◽  
Yang ◽  
Liu ◽  
Liu
Keyword(s):  
Electrostatic Discharge ◽  
Cmos Process ◽  
Silicon Area ◽  
Lateral Dimension ◽  
Esd Protection ◽  
Layout Area ◽  
Protection Capability ◽  
P Type ◽  
Area Efficient

The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.

Fabrication of microbridges in standard complementary metal oxide semiconductor technology

1989 ◽  
Vol 67 (4) ◽  
pp. 184-189 ◽  
Author(s):  
M. Parameswaran ◽  
Lj. Ristic ◽  
A. C. Dhaded ◽  
H. P. Baltes ◽  
W. Allegretto ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Layout Design ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Digital Cmos ◽  
Sensor Applications

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.

1-3 MeV B+ and P+ Implants for C-Mos Technology

1985 ◽  
Vol 45 ◽  
Author(s):  
J. De Pontcharra ◽  
P. Spinelli ◽  
M. Bruel
Keyword(s):  
Doping Level ◽  
Good Control ◽  
Cmos Technology ◽  
High Energy ◽  
Doping Profile ◽  
Cmos Process ◽  
High Doping Level ◽  
Charged Ions ◽  
Channel Region ◽  
Latch Up

ABSTRACTThe need for low temperature processes in VLSI CMOS technology has led to increasing interest in fully implanted wells. In comparison with diffused wells the advantages are good control of the doping profile, low lateral distribution and self-immunity to latch-up.The technique using a medium energy machine with multiple charged ions is not viable in a production context and only high energy machines can be improved to meet the high throughputs required.We have performed boron and phosphorus in the 1 to 3 MeV range on tandem and Van de Graaff machines to prove their effectiveness. Spreading resistance for boron and phosphorus and SIMS for boron are the characterizatton methods uped. The agreement with expected profiles for doses in the 1013 to 1014 /cm2 range is good. We checked the compatibility with a N-well CMOS process: - low doping level at the surface to ensure low capitances and no disturbance of the channel region - high doping level at one micrometer under the surface to lower punchthrough and latch-up effects. The efficiency of masking materials such as Si02 and photoresists is experimentally measured detecting residual doping underneath various thicknesses of the masking pattern. The application to C-MOS technology is discussed.

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