The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology

2016 ◽  
pp. 229-251
Author(s):  
Kavyashree P. ◽  
Siva S. Yellampalli
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Low Voltage Operation ◽  
Common Gate ◽  
Low Power Cmos ◽  
Power Application

In this chapter, an ultra low power CMOS Common Gate LNA (CGLNA) with a Capacitive Cross-Coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the Noise Figure (NF) and power dissipation. In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCC-CGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.

An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure

2019 ◽  
Vol 28 (10) ◽  
pp. 1950172
Author(s):  
Mehdi Bandali ◽  
Alireza Hassanzadeh ◽  
Masoume Ghashghaie ◽  
Omid Hashemipour
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Current Steering ◽  
Ultra Low Power ◽  
Current Cell ◽  
Sample Rate

In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[Formula: see text]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [Formula: see text]-V supply voltage with the sample rate of 140[Formula: see text]MS/s show SFDR [Formula: see text] 64.37[Formula: see text]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.

scholarly journals Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8302
Author(s):  
Cancio Monteiro ◽  
Yasuhiro Takahashi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Process Variations ◽  
Cmos Technology ◽  
Process Technology ◽  
Two Phase ◽  
Ultra Low Power ◽  
Ambient Temperatures

Low-power and secure crypto-devices are in crucial demand for the current emerging technology of the Internet of Things (IoT). In nanometer CMOS technology, the static and dynamic power consumptions are in a very critical challenge. Therefore, the FinFETs is an alternative technology due to its superior attributes of non-leakage power, intra-die variability, low-voltage operation, and lower retention voltage of SRAMs. In this study, our previous work on CMOS two-phase clocking adiabatic physical unclonable function (TPCA-PUF) is evaluated in a FinFET device with a 4-bits PUF circuit complexity. The TPCA-PUF-based shorted-gate (SG) and independent-gate (IG) modes of FinFETs are investigated under various ambient temperatures, process variations, and ±20% of supply voltage variations. To validate the proposed TPCA-PUF circuit, the QUALPFU-based Fin-FETs are compared in terms of cyclical energy dissipation, the security metrics of the uniqueness, the reliability, and the bit-error-rate (BER). The proposed TPCA-PUF is simulated using 45 nm process technology with a supply voltage of 1 V. The uniqueness, reliability, and the BER of the proposed TPCA-PUF are 50.13%, 99.57%, and 0.43%, respectively. In addition, it requires a start-up power of 18.32 nW and consumes energy of 2.3 fJ/bit/cycle at the reference temperature of 27 °C.

scholarly journals Low-noise and low power CMOS photoreceptor using split-length MOSFET

2019 ◽  
Vol 70 (6) ◽  
pp. 480-485
Author(s):  
Jamel Nebhen ◽  
Julien Dubois ◽  
Sofiene Mansouri ◽  
Dominique Ginhac
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Vision Sensor ◽  
Current Consumption ◽  
Low Power Cmos ◽  
Design Requirements ◽  
And Performance

Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor.

scholarly journals A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References

2011 ◽  
Vol 6 (1) ◽  
pp. 7-17
Author(s):  
Dalton Colombo ◽  
Christian Fayomi ◽  
Frederic Nabki ◽  
Luiz F. Ferreira ◽  
Gilson Wirth ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Analog Design ◽  
Voltage Reference ◽  
Inversion Coefficient ◽  
Low Power Cmos ◽  
Traditional Approaches

This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

An Ultra Low-Voltage Ultra Low-Power CMOS Threshold Voltage Reference

2007 ◽  
Vol E90-C (10) ◽  
pp. 2044-2050 ◽  
Author(s):  
L. H.C. FERREIRA ◽  
T. C. PIMENTA ◽  
R. L. MORENO
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Low Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Low Power Cmos

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

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