Scalability of network-on-chip communication architecture for 3-D meshes

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

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Deadlock Free Load Balanced Adaptive Routing for Network on Chip (NoC) Systems

Journal of Computational and Theoretical Nanoscience ◽

10.1166/jctn.2016.5757 ◽

2016 ◽

Vol 13 (10) ◽

pp. 7592-7598

Author(s):

J Kalaivani ◽

B Vinayagasundaram

Keyword(s):

Packet Loss ◽

Probability Function ◽

Adaptive Routing ◽

Network On Chip ◽

Communication Architecture ◽

Data Packets ◽

Oblivious Routing ◽

Simulation Results ◽

On Chip ◽

Load Balanced

The Network-on-Chip (NoC) systems have emerged in on-chip communication architecture in various fields. To achieve excellent results in Network on Chip (NoC) systems application, the routing must eliminate the deadlock issues from the network. To overcome this issue in the network, in this paper, we propose Deadlock Free Load Balanced Adaptive Routing. In this approach, Oblivious Routing (OR) algorithm is implemented on the channel by using the probability function. The network considers the capacity of the node and tries to maximize the throughput based on the connectivity between the data packets flow and minimize the channel load. A Reconfiguration Protocol is used for the data packets to choose other channel in the network if the deadlock occurs. Simulation results show that this approach reduces the delay and packet loss in the network.

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Design of TTL Based Routing Algorithm on UTAR Network on Chip Communication Architecture

International Journal of New Media Technology ◽

10.31937/ijnmt.v5i1.738 ◽

2018 ◽

Vol 5 (1) ◽

pp. 54-57

Author(s):

Wahyudi Khusnandar ◽

Fransiscus Ati Halim ◽

Felix Lokananta

Keyword(s):

Communication Network ◽

Routing Protocol ◽

Routing Algorithm ◽

Adaptive Routing ◽

Network On Chip ◽

Communication Architecture ◽

Traffic Pattern ◽

On Chip ◽

Alternative Routes

XY adaptive routing protocol is a routing protocol used on UTAR NoC communication architecture. This routing algorithm adapts shrotest-path first algorithm, which will forward will not be able to work optimally if the closest route no longer have enough bandwidth to continue the packet. Packet will be stored inside the router and forwarded to the nearest router when closest route has enough bandwidth. This paper suggest TTL based routing algorithm to resolve this issue. TTL based routing algorithm adapts XY adaptive routing protocol by adding several parameters on RTL UTAR NoC and additional bit in each packet sent by router. This additional bit and parameter will be used by TTL based algorithm as additional factors in choosing alternative routes inside the communication architecture. Use of TTL on TTL based routing different from use of TTL on communication network. Packets that carry TTL value that equal to Maximum TTL will be route using XY adaptive routing protocol. TTL based routing algorithm has shown better performance compared to XY adaptive routing on some of the experiment done using MSCL NoC Traffic Pattern Suite. This research also proves that TTL based routing algorithm cannot work optimally on small-scaled architecture.

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Architectural Enhancement of Network on Chip

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.a1054.1291s319 ◽

2019 ◽

Vol 9 (1S3) ◽

pp. 287-290

Keyword(s):

Data Transmission ◽

Architectural Design ◽

Data Communication ◽

Theoretical Data ◽

Network On Chip ◽

Communication Architecture ◽

Serial Data ◽

Design Suggestion ◽

On Chip ◽

Simultaneous Transmission

This paper gives a new architectural design suggestion of NoC, with efficient way of communication. Firstly, to create a serial data communication architecture in competence with the existing widely used parallel form of data transmission and reception [1]. Secondly to enable simultaneous transmission and reception between more than one module at the same time. Thirdly to create the architecture that is modifiable as per the need of user. The theoretical data rate calculated was 300 MBps. The throughput we achieved after the completion is 250MBps.

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A efficacy of different buffer size on latency of network on chip (NoC)

Bulletin of Electrical Engineering and Informatics ◽

10.11591/eei.v8i2.1422 ◽

2019 ◽

Vol 8 (2) ◽

pp. 438-442

Author(s):

Farah Wahida Binti Zulkefli ◽

P. Ehkan ◽

M. N. M. Warip ◽

Ng. Yen. Phing

Keyword(s):

Power Consumption ◽

Semiconductor Industry ◽

Network On Chip ◽

Buffer Size ◽

Large Area ◽

Communication Architecture ◽

Design Time ◽

Network Topologies ◽

On Chip ◽

Scalable Communication

Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.

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PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design

2007 IEEE Workshop on Signal Processing Systems ◽

10.1109/sips.2007.4387596 ◽

2007 ◽

Cited By ~ 3

Author(s):

Nan Wang ◽

Azeez Sanusi ◽

Peiyi Zhao ◽

Shaheen Mohamed ◽

Magdy A. Bayoumi

Keyword(s):

Network On Chip ◽

Architecture Design ◽

Communication Architecture ◽

On Chip

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Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture

2010 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2010.97 ◽

2010 ◽

Cited By ~ 3

Author(s):

Ulhas Deshmukh ◽

Vineet Sahula

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Communication Architecture ◽

Stochastic Automata ◽

On Chip ◽

Automata Network

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SpaceWire Inspired Network-on-Chip Approach for Fault Tolerant System-on-Chip Designs

Dynamic Reconfigurable Network-on-Chip Design ◽

10.4018/978-1-61520-807-4.ch012 ◽

2010 ◽

pp. 293-308

Author(s):

Björn Osterloh ◽

Harald Michalik ◽

Björn Fiethe

Keyword(s):

Fault Tolerant ◽

High Reliability ◽

Dynamic Reconfiguration ◽

Network On Chip ◽

System On Chip ◽

Space Applications ◽

Communication Architecture ◽

Radiation Induced ◽

And Performance ◽

On Chip

Today FPGAs with large gate counts provide a highly flexible platform to implement a complete System-on-Chip (SoC) in a single device. Specifically radiation tolerant space suitable SRAM-based FPGAs have significantly improved the flexibility of high reliable systems for space applications. Currently the reconfigurability of these devices is only used during development phase. A further enhancement would be using the reconfigurability of SRAM-FPGAs in space, either to statically update or dynamically reconfigure processing modules. This is a major improvement in terms of maintenance and performance, which is essential for scientific instruments in space. The requirement for this enhanced system is to guarantee the system qualification and retain the achieved high reliability. Therefore effects during the reconfiguration process and interference of updated modules on the system have to be prevented. Updated modules need to be isolated physically and logically by qualified communication architecture. In this chapter the advantage of a specialized Network-on-Chip architecture to achieve a high reliable SoC with dynamic reconfiguration capability is presented. The requirements for SoC based on SRAM-FPGA in high reliable applications are outlined. Additionally the influences of radiation induced particles are described and effects during the dynamic reconfiguration are discussed. A specialized Network-on-Chip architecture is then proposed and its advantages are presented.

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Application driven evaluation of network on chip architectures forcation parallel signal processing

Advances in Radio Science ◽

10.5194/ars-2-181-2004 ◽

2005 ◽

Vol 2 ◽

pp. 181-186

Author(s):

C. Neeb ◽

M. J. Thul ◽

N. Wehn

Keyword(s):

Signal Processing ◽

Turbo Codes ◽

Communication Complexity ◽

Forward Error Correction ◽

Routing Algorithm ◽

Network On Chip ◽

Parallel Architectures ◽

Error Correction Codes ◽

Communication Architecture ◽

On Chip

Abstract. Today’s signal processing applications exhibit steadily increasing throughput requirements which can be achieved by parallel architectures. However, efficient communication is mandatory to fully exploit their parallelism. Turbo-Codes as an instance of highly efficient forward-error correction codes are a very good application to demonstrate the communication complexity in parallel architectures. We present a network-on-chip approach to derive an optimal communication architecture for a parallel Turbo-Decoder system. The performance of such a system significantly depends on the efficiency of the underlying interleaver network to distribute data among the parallel units. We focus on the strictly orthogonal n-dimensional mesh, torus and k-ary-n cube networks comparing deterministic dimension-order and partially adaptive negative- first and planar-adaptive routing algorithms. For each network topology and routing algorithm, input- and output-queued packet switching schemes are compared on the architectural level. The evaluation of candidate network architectures is based on performance measures and implementation cost to allow a fair trade-off.

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