scholarly journals A efficacy of different buffer size on latency of network on chip (NoC)

2019 ◽  
Vol 8 (2) ◽  
pp. 438-442
Author(s):  
Farah Wahida Binti Zulkefli ◽  
P. Ehkan ◽  
M. N. M. Warip ◽  
Ng. Yen. Phing
Keyword(s):  
Power Consumption ◽  
Semiconductor Industry ◽  
Network On Chip ◽  
Buffer Size ◽  
Large Area ◽  
Communication Architecture ◽  
Design Time ◽  
Network Topologies ◽  
On Chip ◽  
Scalable Communication

Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

Deadlock Free Load Balanced Adaptive Routing for Network on Chip (NoC) Systems

2016 ◽  
Vol 13 (10) ◽  
pp. 7592-7598
Author(s):  
J Kalaivani ◽  
B Vinayagasundaram
Keyword(s):  
Packet Loss ◽  
Probability Function ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Communication Architecture ◽  
Data Packets ◽  
Oblivious Routing ◽  
Simulation Results ◽  
On Chip ◽  
Load Balanced

The Network-on-Chip (NoC) systems have emerged in on-chip communication architecture in various fields. To achieve excellent results in Network on Chip (NoC) systems application, the routing must eliminate the deadlock issues from the network. To overcome this issue in the network, in this paper, we propose Deadlock Free Load Balanced Adaptive Routing. In this approach, Oblivious Routing (OR) algorithm is implemented on the channel by using the probability function. The network considers the capacity of the node and tries to maximize the throughput based on the connectivity between the data packets flow and minimize the channel load. A Reconfiguration Protocol is used for the data packets to choose other channel in the network if the deadlock occurs. Simulation results show that this approach reduces the delay and packet loss in the network.

scholarly journals Design of Smart Power-Saving Architecture for Network on Chip

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Trong-Yen Lee ◽  
Chi-Han Huang
Keyword(s):  
Power Consumption ◽  
Power Saving ◽  
Network On Chip ◽  
Low Power Consumption ◽  
Data Loss ◽  
Smart Power ◽  
Low Area ◽  
Virtual Channels ◽  
On Chip ◽  
Data Transferring

In network-on-chip (NoC), the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in router are included. However, the router includes five I/O ports, and then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, Smart Power-Saving (SPS), for low power consumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors to dynamically save power and optimization area in NoC. Comparison with related works, the new proposed method reduces 37.31%, 45.79%, and 19.26% on power consumption and reduces 49.4%, 25.5% and 14.4% on area, respectively.

scholarly journals Design of TTL Based Routing Algorithm on UTAR Network on Chip Communication Architecture

2018 ◽  
Vol 5 (1) ◽  
pp. 54-57
Author(s):  
Wahyudi Khusnandar ◽  
Fransiscus Ati Halim ◽  
Felix Lokananta
Keyword(s):  
Communication Network ◽  
Routing Protocol ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Communication Architecture ◽  
Traffic Pattern ◽  
On Chip ◽  
Alternative Routes

XY adaptive routing protocol is a routing protocol used on UTAR NoC communication architecture. This routing algorithm adapts shrotest-path first algorithm, which will forward will not be able to work optimally if the closest route no longer have enough bandwidth to continue the packet. Packet will be stored inside the router and forwarded to the nearest router when closest route has enough bandwidth. This paper suggest TTL based routing algorithm to resolve this issue. TTL based routing algorithm adapts XY adaptive routing protocol by adding several parameters on RTL UTAR NoC and additional bit in each packet sent by router. This additional bit and parameter will be used by TTL based algorithm as additional factors in choosing alternative routes inside the communication architecture. Use of TTL on TTL based routing different from use of TTL on communication network. Packets that carry TTL value that equal to Maximum TTL will be route using XY adaptive routing protocol. TTL based routing algorithm has shown better performance compared to XY adaptive routing on some of the experiment done using MSCL NoC Traffic Pattern Suite. This research also proves that TTL based routing algorithm cannot work optimally on small-scaled architecture.

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

scholarly journals Lightweight Cryptography for Network-on-Chip Data Encryption

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Riadh Ayachi ◽  
Ayoub Mhaouch ◽  
Abdessalem Ben Abdelali
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Network Performance ◽  
High Reliability ◽  
Data Encryption ◽  
Network On Chip ◽  
Security Problem ◽  
Finite State ◽  
On Chip ◽  
Main Component

System-on-chip (SoC) is the main processor for most recent applications such as the Internet of things (IoT). SoCs are composed of multiple blocks that communicate with each other through an integrated router. Data routing from a block to another poses many challenges. The network-on-chip (NoC) was used for the transmission of data from a source to a destination with high reliability, high speed, low power consumption, and low hardware occupation. An NoC is composed of a router, network links (NL), and network interface (NI). The main component of the NoC, the NI, is composed of an input/output FIFO, a finite state machine (FSM), pack, and depack modules. Data transmission from a block to another poses a security problem such as secret information extraction. In this paper, we proposed a data encryption framework for NoC based on a light encryption device (LED) algorithm. The main advantages of the proposed algorithm are to reduce the implementation area and to achieve high speed while reducing the power consumption. The proposed encryption framework was simulated Verilog/VHDL on the Xilinx ISE and implemented on the Xilinx Virtex 5 XC5VFX200T. The obtained results have shown that the proposed framework has a smaller area and higher speed compared to existing works. The proposed algorithm has reduced the NI implementation area and enhanced the network performance in terms of speed and security.

Network-on-Chip Especially for Video Coding Applications Using Multilayer Mesh Topology

2019 ◽  
Vol 12 (3) ◽  
pp. 247-256
Author(s):  
Kamel Messaoudi ◽  
Salah Toumi ◽  
El-Bay Bourennane
Keyword(s):  
Video Coding ◽  
Communication System ◽  
Data Transfer ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Topology ◽  
Global Interconnects ◽  
And Performance ◽  
On Chip ◽  
Scalable Communication

Background: Network on chip is proposed as new reusable and scalable communication system for applications with important number of IPs. The NoC architecture characteristics are based on several factors: the implementation strategy of IPs, the power dissipation, the placement of IPs, data transfer time, the requirements of the given application, etc. The N×M Mesh topology combined with the XY routing algorithm are generally chosen in many studies. Hardware IPs proposed in the literature, for various applications as example video encoders, operates at different frequencies and generally implemented according to several strategies and different bus sizes. Connecting these IPs using the same communication system is very difficult. Methods: In this paper, we present a new topology based on multi-layer mesh topology and adapted for video coding applications. The proposed topology exploits the video coding information regarding groups of cores that communicate through two cores only. The idea is to use a specific NoC for each group of cores and connect the NoCs with bridge in the positions of two communication cores. The choice of parameters in each NoC depends on the characteristic of IPs in the same group in order to maximize communication adaptivity and performance. Results: Synthesis results show that the proposed multi-layer mesh topology NoC uses much less resources than the traditional NxM mesh topology NoC. Conclusion: This reduction in term of resources is assured by the considerable reduction in the length and number of global interconnects, resulting in an increase in the performance and decrease in the power consumption and area of wire limited circuits.

scholarly journals Scalability of network-on-chip communication architecture for 3-D meshes

2009 ◽  
Author(s):  
Awet Yemane Weldezion ◽  
Matt Grange ◽  
Dinesh Pamunuwa ◽  
Zhonghai Lu ◽  
Axel Jantsch ◽  
...  
Keyword(s):  
Network On Chip ◽  
Communication Architecture ◽  
On Chip

scholarly journals Bus Based Synchronization Method for CHIPPER Based NoC

2016 ◽  
Vol 2016 ◽  
pp. 1-11
Author(s):  
D. Muralidharan ◽  
R. Muthaiah
Keyword(s):  
Power Consumption ◽  
Network On Chip ◽  
System On Chip ◽  
Communication Delay ◽  
Worst Case ◽  
Synchronization Method ◽  
Area Overhead ◽  
On Chip

Network on Chip (NoC) reduces the communication delay of System on Chip (SoC). The main limitation of NoC is power consumption and area overhead. Bufferless NoC reduces the area complexity and power consumption by eliminating buffers in the traditional routers. The bufferless NoC design should include live lock freeness since they use hot potato routing. This increases the complexity of bufferless NoC design. Among the available propositions to reduce this complexity, CHIPPER based bufferless NoC is considered as one of the best options. Live lock freeness is provided in CHIPPER through golden epoch and golden packet. All routers follow some synchronization method to identify a golden packet. Clock based method is intuitively followed for synchronization in CHIPPER based NoCs. It is shown in this work that the worst-case latency of packets is unbearably high when the above synchronization is followed. To alleviate this problem, broadcast bus NoC (BBus NoC) approach is proposed in this work. The proposed method decreases the worst-case latency of packets by increasing the golden epoch rate of CHIPPER.

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