Analysis and Assessment of temperature effect on an Open Loop Active Gate Voltage Control of GaN Transistor during Turn-ON and Turn-OFF

The paper investigates the management of drain voltage and current slew rates (i.e., dv/dt and di/dt) of high-speed GaN-based power switches during the transitions. An active gate voltage control (AGVC) is considered for improving the safe operation of a switching cell. In an application of open-loop AGVC, the switching speeds vary significantly with the operating point of the GaN HEMT on either or both current and temperature. A closed-loop AGVC is proposed to operate the switches at a constant speed over different operating points. In order to evaluate the reduction in the electromagnetic disturbances, the common mode currents in the system were compared using the active and a standard gate voltage control (SGVC). The closed-loop analysis carried out in this paper has shown that discrete component-based design can introduce limitations to fully resolve the problem of high switching speeds. To ensure effective control of the switching operations, a response time fewer than 10 ns is required for this uncomplex closed-loop technique despite an increase in switching losses.

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An application of Open-Loop Active Gate Voltage Control for GaN Transistors

2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe) ◽

10.23919/epe.2019.8915506 ◽

2019 ◽

Author(s):

M. L. Beye ◽

J. F. Mogniotte ◽

L. V. Phung ◽

N. Idir ◽

H. Maher ◽

...

Keyword(s):

Gate Voltage ◽

Voltage Control ◽

Open Loop

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A Novel Bond Wire Fault Detection Method for IGBT Modules based on Turn-on Gate Voltage Overshoot

IEEE Transactions on Power Electronics ◽

10.1109/tpel.2020.3047135 ◽

2020 ◽

pp. 1-1

Author(s):

Yanyong Yang ◽

Pinjia Zhang

Keyword(s):

Fault Detection ◽

Gate Voltage ◽

Detection Method ◽

Turn On ◽

Igbt Modules ◽

Bond Wire

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Research on IGBT Series Optimization Method Based on Gate Voltage Control

2018 2nd IEEE Conference on Energy Internet and Energy System Integration (EI2) ◽

10.1109/ei2.2018.8581998 ◽

2018 ◽

Author(s):

Ge Zou ◽

Jianjun Tuo ◽

Yuliang Tong ◽

Nan Zhong ◽

Haiyou Wang ◽

...

Keyword(s):

Gate Voltage ◽

Voltage Control ◽

Optimization Method

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Simulation of Drastic Lag Phenomena in GaAs-Based FETs for Large Voltage Swing

VLSI Design ◽

10.1155/2001/87371 ◽

2001 ◽

Vol 13 (1-4) ◽

pp. 245-249

Author(s):

K. Horio ◽

Y. Mitani ◽

A. Wakabayashi ◽

N. Kurosawa

Keyword(s):

Surface State ◽

Gate Voltage ◽

Current Transient ◽

Drain Voltage ◽

Turn On ◽

Voltage Swing

Turn-on characteristics of GaAs MESFETs and HEMTs are simulated when the gate voltage is changed abruptly. The gate-lag or slow current transient becomes more pronounced when the off-state gate voltage is more negative, because the surface-state effects or substrate-trap effects become more significant. Changes of I–V curves of GaAs MESFETs, when the drain voltage is swept with different speeds, are also simulated. When the swept time is short, the curve shows overshoot-like behavior and the kink disappears, indicating that the I–V characteristics should be quite different between DC and RF conditions.

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Parasitic-Based Active Gate Driver Improving the Turn-On Process of 1.7 kV SiC Power MOSFET

Applied Sciences ◽

10.3390/app11052210 ◽

2021 ◽

Vol 11 (5) ◽

pp. 2210

Author(s):

Bartosz Lasek ◽

Przemysław Trochimiuk ◽

Rafał Kopacz ◽

Jacek Rąbkowski

Keyword(s):

Gate Voltage ◽

Drain Current ◽

Theoretical Background ◽

Dissipated Energy ◽

Feedback Signal ◽

Power Losses ◽

Turn On ◽

Speed Up ◽

Gate Driver ◽

The Right

This article discusses an active gate driver for a 1.7 kV/325 A SiC MOSFET module. The main purpose of the driver is to adjust the gate voltage in specified moments to speed up the turn-on cycle and reduce the amount of dissipated energy. Moreover, an adequate manipulation of the gate voltage is necessary as the gate current should be reduced during the rise of the drain current to avoid overshoots and oscillations. The gate voltage is switched at the right moments on the basis of the feedback signal provided from a measurement of the voltage across the parasitic source inductance of the module. This approach simplifies the circuit and provides no additional power losses in the measuring circuit. The paper contains the theoretical background and detailed description of the active gate driver design. The model of the parasitic-based active gate driver was verified using the double-pulse procedure both in Saber simulations and laboratory experiments. The active gate driver decreases the turn-on energy of a 1.7 kV/325 A SiC MOSFET by 7% comparing to a conventional gate driver (VDS = 900 V, ID = 270 A, RG = 20 Ω). Furthermore, the proposed active gate driver lowered the turn-on cycle time from 478 to 390 ns without any serious oscillations in the main circuit.

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