LLFI: An Intermediate Code-Level Fault Injection Tool for Hardware Faults

To verify the validity of fault control measures, a verification platform with software fault injection and hardware fault injection is developed to conduct fault diagnosis measures for MCU control system. For the faults occurring in the internal units of a controller, program debugger is employed to simulate software or hardware faults by varying the data; for the faults occurring in peripheral circuits, a circuit of fault-settings is employed to simulate hardware faults, i.e., open-/short-circuit and electrical level variation. This verification platform is applied to evaluate software measures to control the faults/errors in accordance with IEC60335/IEC60730/UL1998/CSA22.2.08, and a case of induction cooker is presented shows how it works. Experimental results show that the verification platform runs stably and accurately, and has a big value in practice.

Download Full-text

Designing and Validation of Error Detection Software

International Journal of Reliability Quality and Safety Engineering ◽

10.1142/s0218539398000297 ◽

1998 ◽

Vol 05 (04) ◽

pp. 337-357

Author(s):

Sean. J. Geoghegan ◽

D. R. Avresky

Keyword(s):

Error Detection ◽

Fault Injection ◽

Fault Coverage ◽

Detection Techniques ◽

Different Types ◽

Current Program ◽

Program Flow ◽

Detection Software ◽

Hardware Faults ◽

Future Program

We propose a systematic approach for design and validation of error detection software. Formally, the semantic of a specification is represented by a transition system. This representation is then used to generate a flowgraph or ddgraph which is used to construct an execution path tree. The information obtained from this algorithm representation is used to aid in the design of software-based fault detection techniques for hardware faults. Flowgraph and ddgraph representations provide information to predict future program flow. During execution, the current program path is recorded, along with the expected path. Checks are placed to verify that the program path follows the predicted path. Algorithm-based fault tolerance (ABFT) techniques are used to detect data structure corrupting faults and to improve the fault coverage. Fault coverage provided by this approach for different types of hardware faults has been estimated through experiments with the software-based fault injection tool (SOFIT) and the data is presented to demonstrate the effectiveness of the method.

Download Full-text

ACIMS: Analog CIM Simulator for DNN Resilience

Electronics ◽

10.3390/electronics10060686 ◽

2021 ◽

Vol 10 (6) ◽

pp. 686

Author(s):

Dong Ding ◽

Lei Wang ◽

Zhijie Yang ◽

Kai Hu ◽

Hongjun He

Keyword(s):

Energy Efficient ◽

Fault Injection ◽

Experimental Results ◽

Hardware Accelerators ◽

The Real ◽

Analog Computing ◽

Real Hardware ◽

Computationally Intensive ◽

Hardware Faults

Analog Computing In Memory (ACIM) combines the advantages of both Compute In Memory (CIM) and analog computing, making it suitable for the design of energy-efficient hardware accelerators for computationally intensive DNN applications. However, their use will introduce hardware faults that decrease the accuracy of DNN. In this work, we take Sandwich-Ram as the real hardware example of ACIM and are the first to propose a fault injection and fault-aware training framework for it, named Analog Computing In Memory Simulator (ACIMS). Using this framework, we can simulate and repair the hardware faults of ACIM. The experimental results show that ACIMS can recover 91.0%, 93.7% and 89.8% of the DNN’s accuracy drop through retraining on the MNIST, SVHN and Cifar-10 datasets, respectively; moreover, their adjusted accuracy can reach 97.0%, 95.3% and 92.4%.

Download Full-text

Programming-level and redundancy-free method for enhancing software reliability against transient errors in hardware

International Journal of Reliability Quality and Safety Engineering ◽

10.1142/s0218539321500388 ◽

2021 ◽

Author(s):

Bahman Arasteh ◽

Reza Solhi

Keyword(s):

Software Reliability ◽

Supply Voltage ◽

Fault Injection ◽

Soft Errors ◽

Transient Errors ◽

Radiation Induced ◽

And Performance ◽

Hardware Faults ◽

Program Reliability ◽

Recovery Blocks

Software play remarkable roles in different critical applications. On the other hand, due to the shrinking of transistor size and reduction in supply voltage, radiation-induced transient errors (soft errors) have become an important source of computer systems failure. As the rate of transient hardware faults increases, researchers have investigated software techniques to control these faults. Performance overhead is the main drawback of software-implemented methods like recovery blocks that use technical redundancy. Enhancing the software reliability against soft errors by utilizing inherently error masking (invulnerable) programming structures is the main goal of this study. During the programming phase and at the source code level, programmers can select different storage classes such as automatic, global, static and register for the data into their program without paying attention to their inherent reliability. In this study, the inherent effects of these storage classes on the program reliability are investigated. Extensive series of profiling and fault-injection experiments were performed on the set of benchmark programs implemented with different storage classes. Regarding the results of experiments, we find that the programs implemented with automatic storage classes have inherently higher reliability than the programs with static and register storage classes without performance overhead. This finding enables the programmers to develop highly reliable programs without technical redundancy and performance overhead.

Download Full-text

Quantifying the Accuracy of High-Level Fault Injection Techniques for Hardware Faults

2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks ◽

10.1109/dsn.2014.2 ◽

2014 ◽

Cited By ~ 62

Author(s):

Jiesheng Wei ◽

Anna Thomas ◽

Guanpeng Li ◽

Karthik Pattabiraman

Keyword(s):

Fault Injection ◽

Injection Techniques ◽

Hardware Faults ◽

High Level

Download Full-text

A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0419 ◽

2019 ◽

Author(s):

Rommel Estores ◽

Karo Vander Gucht

Keyword(s):

Fault Injection ◽

Fault Simulation ◽

Fault Localization ◽

Pattern Generation ◽

Test Coverage ◽

Actual Case ◽

Electrical Failure ◽

Starting Point ◽

Diagnostic Resolution ◽

Diagnosis Approach

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

Download Full-text

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2008p0180 ◽

2008 ◽

Author(s):

T. Kiyan ◽

C. Boit ◽

C. Brillert

Keyword(s):

Laser Pulse ◽

Integrated Circuits ◽

Continuous Wave ◽

Fault Injection ◽

Scan Design ◽

Flip Flop ◽

Laser Stimulation ◽

Scan Chain ◽

P Type ◽

Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

Download Full-text