A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO

2015 ◽  
Vol 764-765 ◽  
pp. 471-475 ◽  
Author(s):  
Wei Bin Yang ◽  
Shao Jyun Xie ◽  
Han Hsien Wang
Keyword(s):  
Current Efficiency ◽  
Operational Amplifier ◽  
Output Voltage ◽  
Input Voltage ◽  
Control Loop ◽  
Load Current ◽  
Digitally Controlled ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor

The new digital control loop of the low-dropout regulator (LDO) is presented. It is composed of coarse tracking circuit and fine tracking circuit, and no external output capacitor is required to stabilize the control loop. The proposed method makes the quiescent current lower than conventional analog LDOs. The operational amplifier of the conventional LDO fails to operate at 0.7V, and the developed digital LDO in 0.18um CMOS achieved the 0.7V input voltage and 0.5V output voltage with 99.99% current efficiency and 2.6-μA quiescent current at 20mA load current. Therefore, the proposed DLDO is suitable for low power applications.

A Three-Stage Coarse-Fine-Tuning Analog-Assisted Digital LDO

2020 ◽  
pp. 2150047
Author(s):  
Lianxi Liu ◽  
Yiwei Chen ◽  
Xufeng Liao ◽  
Junchao Mu ◽  
Yintang Yang
Keyword(s):  
Output Voltage ◽  
Maximum Load ◽  
Input Voltage ◽  
Fine Tuning ◽  
Cmos Process ◽  
Load Current ◽  
Input Range ◽  
Low Dropout Regulator ◽  
Layout Area ◽  
Two Stages

This paper proposes a three-stage coarse-fine-tuning analog-assisted digital low dropout regulator (AAD-LDO) without digital ripple. The digital regulation consists of two stages, which break the accuracy-speed-power trade-off. To further improve transient response, a step-variable counter used in the first stage is designed, which makes sure that the output current can track the load current rapidly. The ripple caused by the digital regulation disappears due to the existence of the analog-assistant stage (in the proposed AAD-LDO). As a result, the AAD-LDO achieves the output voltage with high accuracy. Designed in a 0.18[Formula: see text][Formula: see text]m CMOS process, the proposed AAD-LDO has a layout area of 0.133[Formula: see text]mm. For the input range of 1.2–1.8[Formula: see text]V, the output voltage is 1[Formula: see text]V. The maximum load current is 10[Formula: see text]mA at the input voltage of 1.2[Formula: see text]V. The linear regulation and load regulation are 0.061[Formula: see text]mV/V and 0.0082[Formula: see text]mV/mA, respectively. The over/undershoot is suppressed effectively for a 9.5[Formula: see text]mA load step. The peak current efficiency is 99.78%.

A LOW DROPOUT REGULATOR WITH LOW QUIESCENT CURRENT AND HIGH POWER SUPPLY REJECTION OVER WIDE RANGE OF FREQUENCY FOR SOC

2011 ◽  
Vol 20 (01) ◽  
pp. 1-13 ◽  
Author(s):  
CHENCHANG ZHAN ◽  
WING-HUNG KI
Keyword(s):  
High Power ◽  
Power Supply ◽  
Cmos Process ◽  
High Loop ◽  
Wide Range ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor ◽  
Large Output ◽  
Supply Rejection

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.

Self-Reduction Quiescent Current Low Power Low Dropout Regulator for SoC Application

2012 ◽  
Vol 591-593 ◽  
pp. 2632-2635
Author(s):  
Lee Chu Liang ◽  
Roslina Mohd Sidek
Keyword(s):  
Low Power ◽  
Process Model ◽  
High Efficiency ◽  
System Stability ◽  
Cmos Process ◽  
Output Impedance ◽  
Load Current ◽  
Output Load ◽  
Quiescent Current ◽  
Low Dropout Regulator

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13μm CMOS process model and designed with high efficiency at low output load current.

scholarly journals A Single-Phase Embedded Z-Source DC-AC Inverter

2014 ◽  
Vol 2014 ◽  
pp. 1-8
Author(s):  
Se-Jin Kim ◽  
Young-Cheol Lim
Keyword(s):  
Output Voltage ◽  
Single Phase ◽  
Input Voltage ◽  
Source Voltage ◽  
Output Capacitor

In the conventional DC-AC inverter consisting of two DC-DC converters with unipolar output capacitors, the output capacitor voltages of the DC-DC converters must be higher than the DC input voltage. To overcome this weakness, this paper proposes a single-phase DC-AC inverter consisting of two embedded Z-source converters with bipolar output capacitors. The proposed inverter is composed of two embedded Z-source converters with a common DC source and output AC load. Though the output capacitor voltages of the converters are relatively low compared to those of a conventional inverter, an equivalent level of AC output voltages can be obtained. Moreover, by controlling the output capacitor voltages asymmetrically, the AC output voltage of the proposed inverter can be higher than the DC input voltage. To verify the validity of the proposed inverter, experiments were performed with a DC source voltage of 38 V. By controlling the output capacitor voltages of the converters symmetrically or asymmetrically, the proposed inverter can produce sinusoidal AC output voltages. The experiments show that efficiencies of up to 95% and 97% can be achieved with the proposed inverter using symmetric and asymmetric control, respectively.

Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

2017 ◽  
Vol 26 (12) ◽  
pp. 1750197 ◽  
Author(s):  
Fatemeh Abdi ◽  
Mahnaz Janipoor Deylamani ◽  
Parviz Amiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Load Current ◽  
Rate Enhancement ◽  
Error Amplifier ◽  
Response Enhancement

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18[Formula: see text][Formula: see text]m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5–3.3[Formula: see text]V, the output voltage after 25[Formula: see text][Formula: see text]s with load current of 100[Formula: see text]mA, is determined with ripple less than 1.8[Formula: see text]mV. In sudden changes, the load current at the range 0–100[Formula: see text]mA, and output voltages after a maximum 15.5[Formula: see text][Formula: see text]s with an input voltage of 3.3[Formula: see text]V have the highest ripple in output voltage of 4[Formula: see text]mV.

High Step-Up Boost-Fly-Back Converter with Soft Switching for Photovoltaic Applications

2018 ◽  
Vol 28 (01) ◽  
pp. 1950014
Author(s):  
Ghasem Haghshenas ◽  
Sayyed Mohammad Mehdi Mirtalaei ◽  
Hamed Mordmand ◽  
Ghazanfar Shahgholian
Keyword(s):  
Output Voltage ◽  
Input Voltage ◽  
Magnetic Core ◽  
Soft Switching ◽  
Voltage Gain ◽  
Pv System ◽  
Voltage Stress ◽  
Photovoltaic Applications ◽  
Output Capacitor ◽  
Switch Voltage

In this paper, a novel high step-up single switch DC–DC converter with soft switching is presented. The main application of this converter is the connection of photovoltaic (PV) system to a 400[Formula: see text]V DC-bus. The proposed converter achieves high step-up voltage gain with small duty cycle by a combined boost and fly-back topology. Also, its switch voltage stress is lower than the output voltage. Besides, in the proposed converter, any auxiliary switch or magnetic core has not been used — therefore, the number of converter components has not been increased much in comparison with the conventional boost-fly-back converter. The operation principles of the converter and its theoretical operation waveforms are presented. In order to evaluate the theoretical analysis, a prototype of the converter is designed and experimentally implemented. The practical results are presented for a 100[Formula: see text]W boost-fly-back converter with input voltage of 40[Formula: see text]V and output voltage of 400[Formula: see text]V. Also, the output capacitor is designed to have less than 1% ripple on output voltage.

scholarly journals Optimal IP Current Controller Design Based on Small Signal Stability for THD Reduction of High-Power Density PFC Boost Converter

2020 ◽  
Author(s):  
Ahmed H. Okilly ◽  
Jeihoon Baek
Keyword(s):  
High Power ◽  
Input Voltage ◽  
Current Control ◽  
Input Current ◽  
High Power Density ◽  
Control Loop ◽  
Dc Voltage ◽  
Control Loops ◽  
Voltage Sensors ◽  
Digitally Controlled

This paper presents an optimal design for the inner current control loop of the continuous current conduction mode (CCM) power factor correction (PFC) stage, which it can be used as the front stage of the two stages alternating current-direct current (AC-DC) telecom power supply. Conventional single-phase CCM-PFC boost converter usually implemented with using of the proportional-integral (PI) controllers in both of the voltage and current control loops, to regulate the output DC voltage to the specified value, moreover to maintains the input current follows the input voltage which offers converter with high power factor (P.F) and low current total harmonic distortion (THD). However, due to the slow dynamic response of the PI controller at the zero-crossing point of the input supply current, input current can’t fully follow the input voltage which leads to high THD. Digitally controlled PFC converter with an optimal design of the inner current control loop using doubly control loops IP controller to reduce the THD and to offer input current with unity P.F was performed in this paper. Furthermore, for the economic design of the digitally control PFC converter, two isolated AC and DC voltage sensors are proposed and designed for the interfacing with the microcontroller unit (MCU). PSIM software was used to test the converter performance with using the proposed designed current controllers and isolated voltage sensors. High power density digitally controlled telecom PFC stage with P.F of about 99.93%, full load efficiency of about 98.70% and THD less 5.50% is achieved in this work.

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