TCAD simulations of dual gate N+ pocket based dopingless tunnel field effect transistor

Author(s):  
Eslavath Raja Naik ◽  
Sudakar Singh Chauhan ◽  
Gaurav Verma
2021 ◽  
Author(s):  
Xueke Wang ◽  
Yabin Sun ◽  
Ziyu Liu ◽  
Yun Liu ◽  
Xiaojin Li ◽  
...  

Abstract In this paper, a novel nanotube tunneling field-effect transistor (NT-TFET) with bias-induced electron-hole bilayer (EHBNT-TFET) is proposed for the first time. By the intentional misalignment and an asymmetric bias configuration of the inner-gate and outer-gate, the line tunneling takes place inside the channel, significantly improving the tunneling rate and area. The device principle and performance are investigated by calibrated 3-D TCAD simulations. Compared to the conventional NT-TFET, the proposed EHBNT-TFET exhibits an increased ON-state current (ION) about 57.2 times and a sub-60 mV/dec subthreshold swing for seven orders of magnitude of drain current. Furthermore, the increased ION and reduced gate capacitance achieve improved dynamic performance. Compared with conventional NT-TFET, the intrinsic delay decreased about 142 times is obtained in EHBNT-TFET.


2021 ◽  
Vol 7 (1) ◽  
Author(s):  
Priyadarshini N D ◽  
Nayana G H ◽  
P Vimala

Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutting-edge low force and super low force semiconductors to substitute the conventional FETs. TFET will be able to provide steep inverse subthreshold swing slope also maintaining a low leakage current, making it an essential structure for limiting the power consumption in Metal Oxide Semiconductor FETs.In this paper, we are simulating different structures of TFET by varying source material to boost the ON current of the device. The different models are designed and simulated using Silvaco TCAD simulator and transfer characteristics are studied.


2020 ◽  
Vol 20 (7) ◽  
pp. 4182-4187
Author(s):  
Ye Sung Kwon ◽  
Seong-Hyun Lee ◽  
Yoon Kim ◽  
Garam Kim ◽  
Jang Hyun Kim ◽  
...  

The tunnel field-effect transistor (TFET) with surrounding channel nanowire (SCNW) structure promises better performance than the conventional planar TFET in terms of subthreshold swing (SS) and on-current (ION). In spite of the advantages of SCNW TFET, there are some technical issues in the aspects of a hump phenomenon in subthreshold region and a high ambipolar current (IAMB) in off-state. In order to overcome these issues, a novel dual-gate SCNW TFET (DG-SCNW TFET) with differential gate work functions (WFs) and a gate-drain underlap is proposed and studied by using technology computer-aided design (TCAD) simulation. In addition, a hetero-junction with SiGe source is applied to improve the device performance. Finally, it is confirmed that the optimized DG-SCNW TFET shows the remarkable performance comparing with the control device.


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