An on-chip load model for off-chip PDN analysis considering interdependency between supply voltage, current profile and clock latency

2018 ◽  
Author(s):  
Jun Chen ◽  
Toshiki Kanamoto ◽  
Hajime Kando ◽  
Masanori Hashimoto
Keyword(s):  
Supply Voltage ◽  
Current Profile ◽  
Load Model ◽  
On Chip ◽  
Chip Load

scholarly journals Dynamic load modeling of some low voltage devices

2009 ◽  
Vol 22 (1) ◽  
pp. 61-70 ◽  
Author(s):  
Lidija Korunovic ◽  
Dobrivoje Stojanovic
Keyword(s):  
Induction Motor ◽  
Dynamic Load ◽  
Low Voltage ◽  
Supply Voltage ◽  
Incandescent Lamp ◽  
Mercury Lamp ◽  
Load Modeling ◽  
Load Model ◽  
Fluorescent Lamps

This paper presents the results of dynamic load modeling for some frequently used low voltage devices. The modeling of long-term dynamics is performed on the basis of step changes of supply voltage of the heater, incandescent lamp, mercury lamp, fluorescent lamps, refrigerator, TV set and induction motor. Parameters of dynamic exponential load model of these load devices are identified, analyzed and mutually compared.

scholarly journals A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI

2012 ◽  
Vol 47 (8) ◽  
pp. 1935-1945 ◽  
Author(s):  
Noah Sturcken ◽  
Michele Petracca ◽  
Steven Warren ◽  
Paolo Mantovani ◽  
Luca P. Carloni ◽  
...  
Keyword(s):  
Network On Chip ◽  
Voltage Regulator ◽  
Nonlinear Feedback ◽  
On Chip ◽  
Chip Load

A ΣΔ MODULATOR USING GAIN-BOOST CLASS-C INVERTER FOR AUDIO APPLICATIONS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340024
Author(s):  
HAO LUO ◽  
YAN HAN ◽  
RAY C. C. CHEUNG ◽  
TIANLIN CAO ◽  
XIAOPENG LIU ◽  
...  
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Signal To Noise ◽  
Dc Gain ◽  
Micro Power ◽  
Class C ◽  
On Chip ◽  
Σδ Modulator

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

2017 ◽  
Vol 26 (10) ◽  
pp. 1750146
Author(s):  
Suresh Alapati ◽  
Sreehari Rao Patri ◽  
K. S. R. Krishna Prasad
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Transient Performance ◽  
Linear Regulator ◽  
Current Change ◽  
Load Regulation ◽  
Low Dropout Regulator ◽  
On Chip ◽  
Fast Rise ◽  
Fixed Bias

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6[Formula: see text]V, dropout voltage of 200[Formula: see text]mV and a quiescent current of 64.4[Formula: see text][Formula: see text]A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95[Formula: see text]mV for a load current changes from 0[Formula: see text]mA to 100[Formula: see text]mA and an overshoot of 150.1[Formula: see text]mV for a current change of 100–0[Formula: see text]mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6[Formula: see text][Formula: see text]V/mA and power supply rejection (PSR) of [Formula: see text]47.8[Formula: see text]dB@ 10[Formula: see text]kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180[Formula: see text]nm UMC CMOS process is employed.

On-Chip Supply Voltage Conversion System and Its Application to a 4Mb DRAM

1986 ◽  
Author(s):  
Yohji WATANABE ◽  
Shigeyoshi WATANABE ◽  
Takashi OHSAWA ◽  
Tohru FURUYAMA ◽  
Kazunori OHUCHI
Keyword(s):  
Supply Voltage ◽  
Conversion System ◽  
On Chip ◽  
Voltage Conversion

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim

2015 ◽  
Vol 25 (03) ◽  
pp. 1640018
Author(s):  
Kishore Duganapalli ◽  
Ajoy K. Palit ◽  
Walter Anheier
Keyword(s):  
Supply Voltage ◽  
Fitness Function ◽  
Vlsi Design ◽  
Pattern Generation ◽  
Test Automation ◽  
Process Technology ◽  
Noise Margin ◽  
Aspect Ratios ◽  
On Chip ◽  
Test Vectors

With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to noise because of the reduction of noise margin. The genetic algorithms (GAs) have been applied earlier in different engineering disciplines as potentially good optimization tools and for various applications in VLSI design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at-faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.

80-GHz-band low-power sub-harmonic mixer IC with a bottom-LO-configuration in 130-nm SiGe BiCMOS

2016 ◽  
Vol 8 (4-5) ◽  
pp. 703-712
Author(s):  
Xin Yang ◽  
Xiao Xu ◽  
Takayuki Shibata ◽  
Toshihiko Yoshimasu
Keyword(s):  
Supply Voltage ◽  
Current Source ◽  
Conversion Gain ◽  
Power Requirement ◽  
Harmonic Mixer ◽  
W Band ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
On Chip ◽  
Marchand Balun

In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only −7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.

0.1μm Technology and Beol

1996 ◽  
Vol 427 ◽  
Author(s):  
Tak H. Ning
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
The Core ◽  
Decoupling Capacitor ◽  
On Chip ◽  
Physical Dimensions

AbstractIt is clear that, at the device level, CMOS is scaleable to 0.1 μm and beyond, provided that the power supply voltage and the device physical dimensions are reduced in some coordinated manner. Contacting these devices and connecting them into circuits, and wiring the circuits at the chip level will become ever more challenging. Furthermore, the integration level of 0.1-μm technology is such that the chip will be the system or at least the core of the system. Thus, the BEOL will not be just for interconnecting the circuits on the chip, but provide the interconnect functions that are presently on the package and/or the board. To this end, copper and low-ε inter-level dielectric, on-chip decoupling capacitor, as well as wire-level hierarchy, will be needed.

Research on Timing of on-Chip Power Supply Noise with Analysis of Scientific Data Materials

2013 ◽  
Vol 310 ◽  
pp. 494-497
Author(s):  
Xiao Guang Li
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Timing Analysis ◽  
Logic Gates ◽  
Scientific Data ◽  
New Method ◽  
Power Supply Noise ◽  
Supply Noise ◽  
On Chip

Aiming at the problems of the influence in power-supply variations on timing analysis, this paper presents a new method to assign a supply-dependent hold margin based on analysis of scientific data materials, which describe a method to accurately characterize logic gates for the sensitivity of delay on supply-voltage variations, and then the method use a commercial microcontroller as a design example. Experiment results shows that the new method with analysis of scientific materials can get a good performance, even under the existing noise.

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