Design of a Radix-2m Hybrid Array Multiplier Using Carry Save Adder

2005 ◽  
Author(s):  
M. Fonseca ◽  
E. da Costa ◽  
S. Bampi ◽  
J. Monteiro
Keyword(s):  
Array Multiplier

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier

Error Compensation Techniques for Fixed-Width Array Multiplier Design — A Technical Survey

2016 ◽  
Vol 26 (03) ◽  
pp. 1730003 ◽  
Author(s):  
S. Balamurugan ◽  
P. S. Mallick
Keyword(s):  
Error Compensation ◽  
Absolute Error ◽  
Mean Square ◽  
Maximum Absolute Error ◽  
Comprehensive Review ◽  
Related Research ◽  
Error Formula ◽  
Error Metrics ◽  
Array Multiplier ◽  
Future Work

This paper provides a comprehensive review of various error compensation techniques for fixed-width multiplier design along with its applications. In this paper, we have studied different error compensation circuits and their complexities in the fixed-width multipliers. Further, we present the experimental results of error metrics, including normalized maximum absolute error [Formula: see text], normalized mean error [Formula: see text] and normalized mean-square error [Formula: see text] to evaluate the accuracy of fixed-width multipliers. This survey is intended to serve as a suitable guideline and reference for future work in fixed-width multiplier design and its related research.

A 4-bit array multiplier design by reversible logic

2015 ◽  
pp. 5-8
Author(s):  
Junzhou Qian ◽  
Junchao Wang
Keyword(s):  
Reversible Logic ◽  
Array Multiplier

scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

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