scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

scholarly journals IMPLEMENTATION OF ELECTRONIC DEVICES OF CMOS FULL ADDER IN LOW POWER VLSI CIRCUITS

2021 ◽  
Vol 2089 (1) ◽  
pp. 012081
Author(s):  
P. Durgaprasadarao ◽  
K.V. Daya Sagar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Electricity Consumption ◽  
Basic Feature ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Total Power ◽  
Electronic Systems ◽  
Power Characteristics ◽  
Total Power Consumption

Abstract Battery-powered devices (for example, mobile phones, digital personal aids, etc) are increasing on the mobile electronic systems market by developing microelectronic circuits with low energy dissipation. The problem of dissipating power could limit the flexibility of the computer system, as the chip’s density and complexity keep on increasing. The power supply consumes approximately 35% of the chip power, particularly at the nanometer level. The purpose of this project is to investigate the efficiency of one of the most reliable low power concepts called Power Gating. It is only nanometer-scale CMOS devices that are the most common technology in existing VLSI systems. Leakage power has become an integral component of total power in the nanometer technology regime. The ALU’s basic feature unit is Full Adder. The electricity consumption of an ALU is decreased by decreasing the energy consumption of an ALU, and an ALU will reduce the power consumption by decreasing the total power consumption. So these days, the complete adder designs are becoming more common with low power characteristics. The proposed project shows the concept of the micro wind tool for low power less transistors.

A 0.8 V 48 μW 82 dB SNDR 10-kHz BANDWIDTH ΣΔ MODULATOR IN 0.13-μM CMOS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350027 ◽  
Author(s):  
WEI LANG ◽  
PEIYUAN WAN ◽  
PINGFEN LIN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Sampling Rate ◽  
Weighted Averaging ◽  
Total Power ◽  
Feed Forward ◽  
Op Amp ◽  
Total Power Consumption ◽  
Σδ Modulator

This paper presents a low-power low-voltage chopper stabilized discrete-time second-order feed-forward ΣΔ modulator with an asynchronous 4-bit successive-approximation-register (SAR) quantizer. The feed-forward topology will reduce the internal signal swing, relaxing the linearity and slew rate requirements for an operational amplifier (op-amp). The analog weighted summation of feed-forward paths is merged with the sampling capacitor array of a SAR quantizer to minimize the distortion and associated hardware overhead. To achieve low power consumption, a partially switched op-amp bias in weak inversion is used for the first integrator. The energy efficiency is further improved by the asynchronous SAR 4-bit quantizer. Moreover, the asynchronous scheme will reduce loop delay caused by the summation block, the quantizer and the data weighted averaging (DWA) circuit, improving circuit stability and lowering power consumption. A 0.13-μm CMOS experimental prototype achieves 84 dB dynamic range, 84 dB peak SNR and 82 dB peak SNDR over an input signal bandwidth of 10-kHz. The total power consumption of the modulator is 48 μW from a 0.8 V supply at an 800-kHz sampling rate.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

FLOORPLAN DESIGN WITH LOW POWER CONSIDERATIONS

1996 ◽  
Vol 07 (02) ◽  
pp. 305-322
Author(s):  
KAI-YUAN CHAO ◽  
D. F. WONG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Network Size ◽  
Total Power ◽  
Wire Length ◽  
Performance Requirements ◽  
Total Power Consumption ◽  
Distribution Of Power ◽  
The Cost

In this paper, a floorplanner for low power design is presented. Our objective is to optimize total power consumption and area during the selection and placement of various implementations for circuit modules. Furthermore, the proposed method considers performance requirements, power line noises, and distribution of power consumption in order to generate lower and evenly distributed power dissipation over the resulting circuit floorplan with a specified performance. For a set of benchmark circuits we tested, on the average, our floorplanner can achieve decreases of total power consumption, wire-length, and power/ground network size by 18.3%, 4.6%, and 24%, respectively, at the cost of an area increase of 8.8% when compared with an existing area/wire-length driven floorplanner.

scholarly journals A Hardware Approach of a Low-Power IoT Communication Interface by NXP FlexIO Module

2019 ◽  
Vol 25 (6) ◽  
pp. 35-39
Author(s):  
Libor Chrastecky ◽  
Jaromir Konecny ◽  
Martin Stankus ◽  
Michal Prauzek
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Total Power ◽  
Processing Unit ◽  
Embedded Devices ◽  
Communication Interface ◽  
Result Section ◽  
Central Processing ◽  
Total Power Consumption ◽  
Software And Hardware

This article describes implementation possibilities of specialized microcontroller peripherals, as hardware solution for Internet of Things (IoT) low-power communication, interfaces. In this contribution, authors use the NXP FlexIO periphery. Meanwhile, RFC1662 is used as a reference communication standard. Implementation of RFC1662 is performed by software and hardware approaches. The total power consumption is measured during experiments. In the result section, authors evaluate a time-consumption trade-off between the software approach running in Central Processing Unit (CPU) and hardware implementation using NXP FlexIO periphery. The results confirm that the hardware-based approach is effective in terms of power consumption. This method is applicable in IoT embedded devices.

scholarly journals CMOS Operational Floating Current Conveyor Circuit for Instrumentation Amplifier Application

2020 ◽  
pp. 317-323
Author(s):  
Fahmi Elsayed ◽  
◽  
Mostafa Rashdan ◽  
Mohammad Salman
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Current Conveyor ◽  
Total Power ◽  
Low Power Consumption ◽  
Instrumentation Amplifier ◽  
Fully Integrated ◽  
Total Power Consumption ◽  
High Bandwidth ◽  
Operational Floating Current Conveyor

This paper presents a fully integrated CMOS Operational Floating Current Conveyor (OFCC) circuit. The proposed circuit is designed for instrumentation amplifier circuits. The CMOS OFCC circuit is designed and simulated using Cadence in TSMC 90 m technology kit. The circuit aims at two different design goals. The first goal is to design a low power consumption circuit (LBW design) while the second is to design a high bandwidth circuit (HBW design). The total power consumption of the LBW design is 1.26 mW with 30 MHz bandwidth while the power consumption of the HBW design is 3 mW with 104.6 MHz bandwidth.

scholarly journals A Low Power Sigma-Delta Modulator with Hybrid Architecture

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5309
Author(s):  
Shengbiao An ◽  
Shuang Xia ◽  
Yue Ma ◽  
Arfan Ghani ◽  
Chan Hwang See ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Total Power ◽  
Cmos Process ◽  
Hybrid Architecture ◽  
Sigma Delta Modulator ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Total Power Consumption

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

scholarly journals A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception

2019 ◽  
Vol 9 (1) ◽  
pp. 3
Author(s):  
Lekbir Cherif ◽  
Mohamed Chentouf ◽  
Jalal Benallal ◽  
Mohammed Darmi ◽  
Rachid Elgouri ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Negative Impact ◽  
Optimization Technique ◽  
Total Power ◽  
Flip Flop ◽  
Physical Implementation ◽  
Total Power Consumption ◽  
Bit Flip ◽  
Implementation Stage

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%.

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