Engineering silicon-on-insulator (SOI) substrates for hybrid orientation technologies (HOT)

2009 ◽  
Author(s):  
T. Signamarcheix ◽  
B. Biasse ◽  
A-M. Papon ◽  
E. Nolot ◽  
B. Ghyselen ◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Soi Substrates

Semi-Insulating Silicon for Microwave Devices

2009 ◽  
Vol 156-158 ◽  
pp. 101-106 ◽  
Author(s):  
Douglas M. Jordan ◽  
Kanad Mallik ◽  
Robert J. Falster ◽  
Peter R. Wilshaw
Keyword(s):  
Room Temperature ◽  
Energy Levels ◽  
Silicon On Insulator ◽  
Microwave Devices ◽  
Insulating Material ◽  
Czochralski Silicon ◽  
Boron Doped ◽  
Microwave Applications ◽  
Soi Substrates ◽  
Phosphorus Doped

The concept of fully encapsulated, semi-insulating silicon (SI-Si), Czochralski-silicon-on-insulator (CZ-SOI) substrates for silicon microwave devices is presented. Experimental results show that, using gold as a compensating impurity, a Si resistivity of order 400 kΩcm can be achieved at room temperature using lightly phosphorus doped substrates. This compares favourably with the maximum of ~180kΩcm previously achieved using lightly boron doped wafers and is due to a small asymmetry of the position of the two gold energy levels introduced into the band gap. Measurements of the temperature dependence of the resistivity of the semi-insulating material show that a resistivity ~5kΩcm can be achieved at 100°C. Thus the substrates are suitable for microwave devices working at normal operating temperatures and should allow Si to be used for much higher frequency microwave applications than currently possible.

Chemical-vapor-deposition growth and characterization of epitaxial 3C–SiC films on SOI substrates with thin silicon top layers

2001 ◽  
Vol 16 (1) ◽  
pp. 24-27 ◽  
Author(s):  
C. K. Moon ◽  
H. J. Song ◽  
J. K. Kim ◽  
J. H. Park ◽  
S. J. Jang ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Chemical Vapor ◽  
Silicon On Insulator ◽  
Significant Shift ◽  
Misfit Dislocations ◽  
Chemical Vapor Deposition Growth ◽  
Hydrogen Flow ◽  
Soi Substrates ◽  
Sic Films

Epitaxial 3C–SiC films were grown by chemical vapor deposition on the silicon-on-insulator (SOI) substrates with 20–75-nm-thick Si top layers. A relatively low growth temperature of 1150 °C and a reduced hydrogen flow rate of 1 lpm during the precarbonization process was necessary to preserve the SOI structure and thereby obtain high-quality SiC films. The transmission electron microscopy observation of the SiC/SOI structures revealed high density of misfit dislocations in the SiC film, but no dislocation within the top Si layer. The x-ray-diffraction results did not show any significant shift of the (400) SiC peak position among the SiC/Si and the SiC/SOI samples. This strongly suggests that the Si top layer is not deformed during the SiC/SOI growth and the strain within the 3C–SiC layer is not critically affected by substituting the Si substrate with the SOI substrate, even when the Si top layer is as thin as 20 nm.

Integration of CMP Fixed Abrasive Polishing into the Manufacturing of Thick Film SOI Substrates

2005 ◽  
Vol 867 ◽  
Author(s):  
Martin Kulawski ◽  
Hannu Luoto ◽  
Kimmo Henttinen ◽  
Tommi Suni ◽  
Frauke Weimar ◽  
...  
Keyword(s):  
Thick Film ◽  
Surface Damage ◽  
Silicon On Insulator ◽  
Thickness Variation ◽  
Process Sequence ◽  
Processing Times ◽  
Early Results ◽  
Total Thickness Variation ◽  
Soi Substrates ◽  
Fixed Abrasive

AbstractThe specification for the total thickness variation (TTV) of the device layers on thick-film silicon on insulator (SOI) wafers tighten for future applications. Therefore, the bulk removal polishing process of current technology after grinding cannot meet the demands in terms of flatness. The currently required amount of material removal for polishing out the induced sub surface damage (SSD) of the grinding is very high. Additionally, slurry-based CMP processes show unsatisfactory grindline and topography removal. This in turn reflects negatively to processing times, throughput and overall flatness performance.Encouraging early results of FA pad use for silicon and SOI polishing have already been further developed [1]. Low SSD grinding has been introduced to silicon manufacturing [[1]]. In this work, an integrated manufacturing process sequence is presented. Starting from low SSD grinding of the bonded SOI wafer couple, an optimized FA CMP step is replacing the conventional bulk polishing with reduced removal. The SSD after FA CMP is investigated by oxide induced stacking fault (OISF) method [[2]] and results are used to adjust the final polishing step of the substrates. The overall process sequence is highly advantageous in terms of performance in TTV and provides a highly competitive and effective method for achieving best possible surface quality with minimized total silicon removal. This method is not only useful for SOI wafers but also in other areas of silicon processing.

scholarly journals Large-Area Resonance-Tuned Metasurfaces for On-Demand Enhanced Spectroscopy

2015 ◽  
Vol 2015 ◽  
pp. 1-7 ◽  
Author(s):  
Masanobu Iwanaga ◽  
Bongseok Choi ◽  
Hideki T. Miyazaki ◽  
Yoshimasa Sugimoto ◽  
Kazuaki Sakoda
Keyword(s):  
Nanoimprint Lithography ◽  
Near Infrared ◽  
Cost Effective ◽  
Silicon On Insulator ◽  
Fine Tuning ◽  
Infrared Range ◽  
Large Area ◽  
Optical Resonance ◽  
Optical Resonances ◽  
Soi Substrates

We show an effective procedure for lateral structure tuning in nanoimprint lithography (NIL) that has been developed as a vertical top-down method fabricating large-area nanopatterns. The procedure was applied to optical resonance tuning in stacked complementary (SC) metasurfaces based on silicon-on-insulator (SOI) substrates and was found to realize structure tuning at nm precision using only one mold in the NIL process. The structure tuning enabled us to obtain fine tuning of the optical resonances, offering cost-effective, high-throughput, and high-precision nanofabrication. We also demonstrate that the tuned optical resonances selectively and significantly enhance fluorescence (FL) of dye molecules in a near-infrared range. FL intensity on a SC metasurface was found to be more than 450-fold larger than the FL intensity on flat Au film on base SOI substrate.

Mechanism for the Reduction of Threading Dislocation Densities in Si0.82Ge0.18 Films on Silicon on Insulator Substrates

2001 ◽  
Vol 673 ◽  
Author(s):  
E.M. Rehder ◽  
T.S. Kuan ◽  
T.F. Kuech
Keyword(s):  
Dislocation Density ◽  
Chemical Vapor ◽  
Dislocation Core ◽  
Extensive Study ◽  
Silicon On Insulator ◽  
Dislocation Dynamics ◽  
Threading Dislocation ◽  
Misfit Dislocations ◽  
Threading Dislocation Density ◽  
Soi Substrates

ABSTRACTWe have made an extensive study of Si0.82Ge0.18 film relaxation on silicon on insulator (SOI) substrates having a top Si layer 40, 70, 330nm, and 10[.proportional]m thick. SiGe films were deposited with a thickness up to 1.2[.proportional]m in an ultrahigh vacuum chemical vapor deposition system at 630°C. Following growth, films were characterized by X-ray diffraction and a dislocation revealing etch. The same level of relaxation is reached for each thickness of SiGe film independent of the substrate structure. Accompanying the film relaxation is the development of a tetragonal tensile strain in the thin Si layer of the SOI substrates. This strain reached 0.22% for the 1.2[.proportional]m film on the 40nm SOI and decreases with SOI thickness. The Si thickness of the SOI substrate also effected the threading dislocation density. For 85% relaxed films the density fell from 7×106 pits/cm2 on bulk Si to 103pits/cm2 for the 40, 70, and 330nm SOI substrates. The buried amorphous layer of the SOI substrate alters the dislocation dynamics by allowing dislocation core spreading or dislocation dissociation. The reduced strain field of these dislocations reduces dislocation interactions and the pinning that results. Without the dislocation pinning, the misfit dislocations can extend longer distances yielding a greatly reduced threading dislocation density.

scholarly journals Simulation of a new hybrid Si/SiC power device for harsh environment applications

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000190-000194
Author(s):  
P.M. Gammon ◽  
C.W. Chan ◽  
P.A. Mawby
Keyword(s):  
Thin Film ◽  
High Temperature ◽  
Silicon On Insulator ◽  
Power Device ◽  
Harsh Environment ◽  
Silicon Thin Film ◽  
Device Structure ◽  
Solar Inverter ◽  
Thermal Simulations ◽  
Soi Substrates

A new power device structure is proposed, conceived to operate in a high temperature, harsh environment, for example within a motor drive application down hole, as an inverter in the engine bay of an electric car, or as a solar inverter in space. The lateral silicon power device resembles a laterally diffused MOSFET (LDMOS), such as those implemented within silicon on insulator (SOI) substrates. However, unlike SOI, the Si thin film has been transferred directly onto a semi-insulating 6H silicon carbide (6H-SiC) substrate via a wafer bonding process. Thermal simulations of the hybrid Si/SiC substrate have shown that the high thermal conductivity of the SiC will have a junction-to-case temperature approximately 4 times less that an equivalent SOI device, reducing the effects of self-heating. Electrical simulations of a 600 V power device, implemented entirely with the silicon thin film, suggest that it will retain the ability of SOI to minimise leakage at high temperature, but does so with 50% less conduction losses.

Sign in / Sign up

Export Citation Format

Share Document