A Novel Manufacturing Process for Glass THGEMs and First Characterisation in an Optical Gaseous Argon TPC

This paper details a novel, patent pending, abrasive machining manufacturing process for the formation of sub-millimetre holes in THGEMs, with the intended application in gaseous and dual-phase TPCs. Abrasive machining favours a non-ductile substrate such as glasses or ceramics. This innovative manufacturing process allows for unprecedented versatility in THGEM substrates, electrodes, and hole geometry and pattern. Consequently, THGEMs produced via abrasive machining can be tailored for specific properties: for example, high stiffness, low total thickness variation, radiopurity, moisture absorption/outgassing and/or carbonisation resistance. This paper specifically focuses on three glass substrate THGEMs (G-THGEMs) made from Schott Borofloat 33 and fused silica. Circular and hexagonal hole shapes are also investigated. The G-THGEM electrodes are made from indium tin oxide (ITO), with a resistivity of 150 Ω/Sq. All G-THGEMs were characterised in an optical (EMCCD) readout GArTPC and compared to a traditionally manufactured FR4 THGEM, with their charging and secondary scintillation (S2) light production behaviour analysed.

The effect of the chuck shape on the wafer topography in back grinding of wafer with outer rim

Back Grinding of Wafer with Outer Rim (BGWOR) is a novel method for carrier-less thinning of silicon wafers. Silicon wafers are widely used in integrated circuits (ICs). The topography of the wafer will not only directly affect the efficiency of subsequent processing of semiconductor devices, but correspondingly affect the performance and life of these devices. However, there are few studies on the shape of the ground wafer in BGWOR. In this paper, the mathematical model of the wafer topography in BGWOR was developed. With this model, the radial thickness and total thickness variation (TTV) of a wafer under different parameters, including inclination angles and radii of grinding wheel for dressing chuck, were simulated by MATLAB. Inclination angles and radii of grinding wheels for the dressing chuck had a great influence on the radial thickness and TTV of a wafer in the BGWOR. Lastly, the pilot experiments were conducted to validate the theoretical model of grinding topography and TTV of the wafer in BGWOR. To enhance the flatness of the ground wafer, it is essential to control the shape of the dressing chuck. The research results are helpful to the optimization of the dressing process of the chuck in the BGWOR.

Vacuum-Assisted Hot-Forming Using Tailored Laminate Temperature

A non-isothermal vacuum assisted hot-forming process using tailored laminate temperature is introduced. By using process simulation and manufacturing experiments, improved laminate quality is achieved compared to the standard hot-forming process. Furthermore, it is also shown that the manufacturing time in the clean room can be reduced to one tenth of the standard process time. In this study 8.4 mm thick quasi-isotropic laminates from unidirectional prepreg were laid up flat with an automatic tape laying machine and hot-formed to a U-shaped laminate. The laminates were then cured in a concave mould with standard bag on the inside. A complete tailored temperature hot-forming cycle of 7.5 min produced a very good final laminate quality with a total thickness variation as low as 4.0% and without wrinkles or indications of porosity. With a 4 min hot-forming cycle the thickness variation was also acceptable at 8%.

Removal Characteristics of Sapphire Lapping using Composite Plates with Consciously Patterned Resinoid-Bonded Semifixed Diamond Grits

Sapphire lapping is of key importance for the successful planarization of wafers that are widely present in electronic devices. However, the high hardness of sapphire makes it extremely challenging to improve its material removal rate during the lapping process without compromising surface quality and dimensional accuracy. In this work, a novel composite lapping plate consisting of a rigid resin frame and flexible sol–gel balls was fabricated with consciously designed patterns. Through lapping experiment, it was revealed that the diamond grits imbedded in the sol–gel balls can effectively lap the sapphire at a promising material removal rate (MRR), without the formation of undesirable scratches and loss of surface integrity. Moreover, by designing the arrangement patterns of sol–gel balls, the total thickness variation (TTV) can also be ensured for lapped sapphire substrates. The implications of experimental results were also discussed based on the trajectory analysis and contact mechanics of lapping grits in order to demonstrate the potential of the newly developed composite abrasive tools for sapphire-lapping applications.

A Study of the Effect of Back Grind Wheels on Wafer Edge Chippings and Die Strength

The drive for thinner package architecture is already becoming a necessity. There were a need of thinner Integrated Circuit or IC in order to fit in to thinner applications like mobile phones. One of the major semiconductor process that enables miniaturization was wafer back grinding. The process involves wafer thinning to a required thickness with the use of back grinding wheels that serve as the abrasive material. The paper will discuss the effect of back grind input parameters like step grinding and wheel grit size to its output characteristics like total thickness variation, edge chippings and die strength. Total thickness variation will define if the new wheel will not affect the variation with the wafer. On the other hand, edge chippings and die strength will define the reliability of the die on different conditions of the package. Lastly, these 3 characteristics will establish the manufacturability of the process as it will eliminate the probability of wafer breakage.

Temporary Bonding Cost Of Ownership: The link between low total thickness variation and chip yield

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed. The presented temporary bonding process consists of a bi-layer system, a release layer, Dow Corning WL-3001 Bonding Release and an adhesive layer, Dow Corning WL-4030 or WL-4050 Bonding Adhesive, processed on EVG's 850XT universal temporary bonding and debonding platform. Furthermore, this bi-layer spin coated material allows a room temperature bonding-debonding process increase process throughput which translates to low cost of ownership for high volume manufacturing. As such, this bi-layer approach features high chemical stability exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. Besides chemical stability this adhesive system provides also a high thermal stability when exposed to temperatures up to 300 °C. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO. In this presentation, we will present a study of the total thickness variation (TTV) and the evolution of TTV at different stages of the process. High resolution in-line metrology is an enabling tool to trace the bond integrity and yield throughout backside processing. As TTV is a major determining factor of the overall process yield, understanding its impact over the bonded wafer pair carries major importance. Especially, non-continuity of the edge region, showing an inherent edge bead after coating, and edge die yield will be focus of our contribution. Finally, our experimental results will be transferred into a cost of ownership model, discussing the pros and cons for high volume production.

Effect of Double Sided Process Parameters in Lapping Silicon Wafer

Silicon wafer is widely used in semiconductor industries for development of sensors and integrated circuit in computer, cell phones and wide variety of other devices. Demand on the device performance requires flatter wafer surface, and less dimensional wafer variation. Prime silicon wafer is hard and brittle material. Due to its properties, double sided lapping machine with ceramic grinding agent were introduced for machining high quality standard silicon wafers. The main focus is the silicon wafer with high accuracy of flatness; to reduce total thickness variation, waviness and roughness. In this paper the lapping experiment and analysis showed that the double sided lapping machine is able to produce total thickness variation less than 10 um at controlled process parameters within short processing time. Machining using low mode method reduced the total thickness variation (TTV) value. The lapping load and speed directly reflected the performance and condition of final silicon wafer quality.

A Novel Method to Modify the Lapping Uniformity for Silicon Wafer

In this paper, a novel lapping method based on regulating the position of carrier centroid is proposed to modify interfacial normal pressure uniformity. Eight special points are selected to represent carrier weight. This lapping process can be divided into initial stage, regulated stage and stable stage. The purpose of initial stage is calculating the position of carrier centroid according to the equivalent mass of eight points. The regulated stage is to decrease total thickness variation (TTV) by regulating the position of weight. Finally, the stable stage will keep uniformity of material removal rate (MRR) uniform at each point. A 3-inch and 400 μm thickness silicon wafer is lapped to demonstrate the feasibility of this method. We can find that TTV of this wafer decreases from initial stage 20 μm to 3 μm and remain constant. Therefore, the uniformity of MRR has been greatly improved by this novel lapping method.

Production Proven, High Precision Temporary Bond/De-bond Process

Wafer thinning represents a critical step in 2.5D and 3D-IC integration. Achieving low total thickness variation (TTV) of a bonded stack is essential since it directly impacts the TTV of the thinned device wafer. It is essential to understand and utilize appropriate processes and materials that provide precision bonded stacks prior to thinning operations in order to achieve high process yields. The 3M™ Wafer Support System and Corning's precision glass carrier wafers were used to produce bonded stacks. Leveraging metrology tools like the Flatmaster MSP-300 and low coherence interferometric probes allow for characterization of the TTV of each layer of a bonded stack and better understanding of the stack-up as well as how to minimize stack TTV. The ability to deliver stack TTV of < 2 um in a repeatable manner has been demonstrated.