Comparison of diodes and resistors for measuring chip temperature during thermal characterization of electronic packages using thermal test chips

2002 ◽  
Author(s):  
A. Claassen ◽  
H. Shaukatullah
Keyword(s):  
Thermal Characterization ◽  
Electronic Packages ◽  
Chip Temperature ◽  
Thermal Test ◽  
Test Chips

A Scalable Multi-Functional Thermal Test Chip Family: Design and Evaluation

2001 ◽  
Vol 123 (4) ◽  
pp. 323-330 ◽  
Author(s):  
Zs. Benedek ◽  
B. Courtois ◽  
G. Farkas ◽  
E. Kolla´r ◽  
S. Mir ◽  
...  
Keyword(s):  
Temperature Sensor ◽  
Thermal Characterization ◽  
Thermal Engineering ◽  
Test Chip ◽  
Basic Cell ◽  
Thermal Test ◽  
Wide Range ◽  
The Family ◽  
Test Chips

Nowadays, thermal characterization of IC packages and packaging technologies is becoming a key task in thermal engineering. To support this by measurements, we developed a family of thermal test chips that allow a wide range of possible applications. Our chips are based on the same basic cell that is mainly covered by dissipating resistors and also contains a temperature sensor. These basic cells are organized into arrays of different size. The arrays are designed such that further “super arrays” can also be built for tiling up larger package cavities. The first members of the family, TMC9 and TMC81, have been manufactured. Our measurements show that the goals aimed at the design have been achieved.

A Simple Method for Thermal Characterization of Stacked Die Electronic Packages in Staggered Arrangement

2018 ◽  
Vol 15 (3) ◽  
pp. 117-125 ◽  
Author(s):  
Bharath R. Bharadwaj ◽  
SriNithish Kandagadla ◽  
Praveen J. Nadkarni ◽  
V. Krishna ◽  
T. R. Seetharam ◽  
...  
Keyword(s):  
Heat Dissipation ◽  
Superposition Principle ◽  
Thermal Characterization ◽  
Electronic Packages ◽  
Heat Sources ◽  
Linear Superposition ◽  
Simple Method ◽  
Ansys Simulation ◽  
Staggered Arrangement

Abstract The need for compactness and efficiency of processing devices has kept increasing rapidly over the past few years. This need for compactness has driven the dice to be stacked one above the other. But with this come the difficulty of heat dissipation and its characterization because there are multiple heat sources and a single effective heat-conductive path. Hence, it becomes important to know the distribution and characterization of heat and temperature to provide effective cooling systems. In this article, we discuss the temperature distribution of various power configurations on stacked dice with five dice, when the dice are in staggered arrangement. The simulations have been carried out for both free convection and forced convection conditions using the ANSYS commercial software. The linear Superposition principle (LSP) is demonstrated on these configurations and validated with the results obtained from ANSYS simulation. LSP can be applied for the quick estimation of die temperatures with negligible error.

Transient Thermal Characterization of a Stacked Multichip Package

2007 ◽  
Vol 4 (1) ◽  
pp. 23-30 ◽  
Author(s):  
Kimmo Kaija ◽  
Pekka Heino
Keyword(s):  
Steady State ◽  
Flip Chip ◽  
Thermal Characterization ◽  
Transient Behavior ◽  
Fe Model ◽  
Thermal Test ◽  
Transient Thermal ◽  
Temperature Responses

This paper is a case study of the thermal behavior of a stacked multichip package (SMCP). The aim is to measure temperature responses when heat is dissipated on different dice and to characterize the behavior with a compact thermal model (CTM) that accurately models steady-state and transient responses with a simple thermal RC -network. The measured package consists of three stacked layers, where each layer has one thinned flip chip attached die on an aramid interposer. The package's thermal responses were measured with thermal test dice that contain heaters and temperature sensors. The package was modeled with a finite element method (FEM) and the simulated temperature responses showed reasonable agreement with measured data. The FE model was further used to provide reference thermal data under different boundary conditions for CTM synthesis. The obtained CTM models accurately the steady-state and transient behavior and can be used as simplified model of the measured SMCP for further thermal analysis.

Thermal Characterization of Electronic Packages Using a Three-Dimensional Fourier Series Solution

2000 ◽  
Vol 122 (3) ◽  
pp. 233-239 ◽  
Author(s):  
J. R. Culham ◽  
M. M. Yovanovich ◽  
T. F. Lemczyk
Keyword(s):  
Fourier Series ◽  
Boundary Conditions ◽  
Series Solution ◽  
Analytical Approach ◽  
Printed Circuit Boards ◽  
Three Dimensional ◽  
Thermal Characterization ◽  
Steady State Solution ◽  
Electronic Packages

The need to accurately predict component junction temperatures on fully operational printed circuit boards can lead to complex and time consuming simulations if component details are to be adequately resolved. An analytical approach for characterizing electronic packages is presented, based on the steady-state solution of the Laplace equation for general rectangular geometries, where boundary conditions are uniformly specified over specific regions of the package. The basis of the solution is a general three-dimensional Fourier series solution which satisfies the conduction equation within each layer of the package. The application of boundary conditions at the fluid-solid, package-board and layer-layer interfaces provides a means for obtaining a unique analytical solution for complex IC packages. Comparisons are made with published experimental data for both a plastic quad flat package and a multichip module to demonstrate that an analytical approach can offer an accurate and efficient solution procedure for the thermal characterization of electronic packages. [S1043-7398(00)01403-1]

Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding

2017 ◽  
Vol 139 (1) ◽  
Author(s):  
Herman Oprins ◽  
Vladimir Cherman ◽  
Tomas Webers ◽  
Abdellah Salahouelhadj ◽  
Soon-Wook Kim ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Measurement Data ◽  
Thermal Characterization ◽  
Test Chip ◽  
Thermal Test ◽  
Wafer Pair ◽  
Transient Measurement

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

Impact of On-Die Discrete Heating on Thermal Performance Characteristics of Silicon Based IC Electronic Packages

1999 ◽  
Author(s):  
V. H. Adams ◽  
K. Ramakrishna
Keyword(s):  
Heat Source ◽  
Heat Generation ◽  
Thermal Characterization ◽  
Electronic Packages ◽  
Heat Sources ◽  
Discrete Heat Sources ◽  
Uniform Heat ◽  
On Chip ◽  
Silicon Based

Abstract Simulations for thermal characterization of electronic packages for silicon-based integrated circuit (IC) components typically assume one of the two uniform heat generation conditions. They are: (1) an isoflux condition in which heat generation is uniformly distributed over the active surface of the die, or (2) a uniform heat generation over the entire (or active) volume of the die. The use of these models may be justified due to high thermal conductivity of silicon, size of the devices on the die, and their relatively uniform spatial distribution over the entire surface of the die in the traditional silicon technologies. However, the current and future technologies are migrating towards embedded systems solutions, such as system-on-chip, and in traditional applications devices are brought in close proximity to each other for improved on-chip electrical performance. These trends result in localized regions of power dissipation on the die that would invalidate the use of traditional uniform generation models in the thermal characterization. The present study examines the effect of discrete heat sources (as opposed to uniformly distributed sources) on the die on thermal performance and characterization of the electronic packages. For this purpose, a conjugate heat transfer problem of a memory chip in a 119 I/O flip chip ceramic and plastic ball grid array (FC-C & PBGA) package under natural and forced convection conditions. First the model is validated against experimentally measured thermal data on a 119 I/O FC-C & P BGA daisy-chain test packages with a thermal test die with uniformly distributed resistive heat source. Junction-to-ambient temperature difference predictions from the simulations are within 10% of the measurements for the uniform heating case. The validated model is then suitably modified to account for discrete heat sources and actual substrates. Results from the discrete heat sources study show a 15–20% increase in predicted junction-to-ambient temperature difference and a larger (a 10–15 °C) temperature variation across the active face of the die than for with a uniform heat source. These results call for the use of discrete heat sources in the thermal characterization of new generation of embedded silicon technologies. They also point to the need for development of test die and characterization methodologies for these technologies with discrete heat sources.

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