Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

Reproducible Reliable AuSi Eutectic Wafer Bond Process With High Yield

The AuSi eutectic bond process is a well known and important technique in the field of single chip packaging. When it comes to low-cost and hermetic sealed packages for MEMS/NEMS sensors and actuators this technology has its decisive merits. The AuSi bonding is a low-temperature process with an electric conductive alloy. To achieve a reliable bonding with 100% yield is quite difficult, especially for large areas. In our institute we made several analyses with different process parameters and surface properties variations. The results show that the surface condition of the silicon side of the wafer pair as well as the process parameters are very important factors in relation to the yield of the eutectic bond. We also did investigations on the thickness of the gold layer. Unlike conventional AuSi wafer bonding technologies [1] our technique does not need several μm thick gold layers. We were able to achieve 100% bond yield with 1500nm and even 150nm thin gold layers. Another result we found was that a good bonding process is not only depending on the value of applied temperature and time, there is also an important influence because of the heat flow and applied pressure. In the presentation we would like to introduce our results and experience, plus we will present the coherences of parameter variations for achieving 100% yield.

Effects of Bonding Process Parameters on Wafer-to-Wafer Alignment Accuracy in Benzocyclobutene (BCB) Dielectric Wafer Bonding

Wafer-level three-dimensional (3D) integration is an emerging technology to increase the performance and functionality of integrated circuits (ICs). Aligned wafer-to-wafer bonding with dielectric polymer layers (e.g., benzocyclobutene (BCB)) is a promising approach for manufacturing of 3D ICs, with minimum bonding impact on the wafer-to-wafer alignment accuracy essential. In this paper we investigate the effects of thermal and mechanical bonding parameters on the achievable post-bonding wafer-to-wafer alignment accuracy for polymer wafer bonding with 200 mm diameter wafers. Our baseline wafer bonding process with softbaked BCB (∼35% cross-linked) has been modified to use partially cured (∼ 43% crosslinked) BCB. The partially cured BCB layer does not reflow during bonding, minimizing the impact of inhomogeneities in BCB reflow under compression and/or slight shear forces at the bonding interface. As a result, the non-uniformity of the BCB layer thickness after wafer bonding is less than 0.5% of the nominal layer thickness and the wafer shift relative to each other during the wafer bonding process is less than 1 μm (average) for 200 mm diameter wafers. The critical adhesion energy of a bonded wafer pair with the partially cured BCB wafer bonding process is similar to that with soft-baked BCB.

200. mm Silicon Wafer-to-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions

ABSTRACTWafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.

Nanofluidic Channel Fabrication and Characterization by Micromachining

The well-established microfabrication techniques of complementary metallic oxide silicon (CMOS) selective oxidation and wafer-wafer fusion bonding were used to fabricate sub-micrometer silicon fluidic channels as small as 30 nm between extremely thin SiO2 top and bottom layers of 30 nm thicknesses. Trenches a few tens of nanometer deep were patterned in 10-cm diameter Si wafers by selective oxidation and their depth measured by atomic force microscopy (AFM); the AFM measured depths showed that the trench depth could be controlled to nanometer resolution. The resolution of the photolithography employed determined the trench width resolution. Nanochannels were formed with direct wafer-wafer fusion bonding. Channels of 30-nm depth or greater between the bonded wafer pair were nondestructively detected by a simple infrared (IR) image system; channels less than this depth collapsed for the overall channel geometry employed. Thus the nanofluidic structures survived the pressure and high temperature anneal of wafer bonding. Experimental results agree well with a theoretical prediction for which depths nanochannels would collapse.