Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications

2020 ◽  
Vol 67 (1) ◽  
pp. 80-89 ◽  
Author(s):  
Soumitra Pal ◽  
Subhankar Bose ◽  
Wing-Hung Ki ◽  
Aminul Islam
Keyword(s):  
Low Power ◽  
Space Applications ◽  
Power Dynamic ◽  
Sram Cell

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

A fully integrated low-power CMOS particle detector front-end for space applications

1998 ◽  
Vol 45 (4) ◽  
pp. 2272-2278 ◽  
Author(s):  
J. Vandenbussche ◽  
F. Leyn ◽  
G. Van der Plas ◽  
G. Gielen ◽  
W. Sansen
Keyword(s):  
Low Power ◽  
Particle Detector ◽  
Space Applications ◽  
Fully Integrated ◽  
Front End ◽  
Low Power Cmos
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