Anti-Screening Effect of Gate-Electrode Holes on Remote Phonon Scattering in InGaZnO Thin-Film Transistors

Author(s):  
Hui Su ◽  
Wing Man Tang ◽  
Pui To Lai
2011 ◽  
Vol 5 (5-6) ◽  
pp. 211-213 ◽  
Author(s):  
Hee Sung Lee ◽  
Chan Ho Park ◽  
Kwang H. Lee ◽  
Dong-Ho Kim ◽  
Hye-Ri Kim ◽  
...  

2009 ◽  
Vol 54 (9(5)) ◽  
pp. 518-522 ◽  
Author(s):  
Jinwoo Kim ◽  
Junhee Cho ◽  
Seungjun Chung ◽  
Jeonghun Kwak ◽  
Changhee Lee ◽  
...  

Materials ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2299
Author(s):  
Hyeon-Jun Lee ◽  
Katsumi Abe ◽  
June-Seo Kim ◽  
Won-Seok Yun ◽  
Myoung-Jae Lee

As novel applications of oxide semiconductors are realized, various structural devices and integrated circuits are being proposed, and the gate-overlay defect phenomenon is becoming more diverse in its effects. Herein, the electrical properties of the transistor that depend on the geometry between the gate and the semiconductor layer are analyzed, and the specific phenomena associated with the degree of overlap are reproduced. In the semiconductor layer, where the gate electrode is not overlapped, it is experimentally shown that a dual current is generated, and the results of 3D simulations confirm that the magnitude of the current increases as the parasitic current moves away from the gate electrode. The generation and path of the parasitic current are then represented visually through laser-enhanced 2D transport measurements; consequently, the flow of the dual current in the transistor is verified to be induced by the electrical potential imbalance in the semiconductor active layer, where the gate electrodes do not overlap.


Author(s):  
Subhash Singh ◽  
Hiroyuki Matsui ◽  
Shizuo Tokito

Abstract We report printed single and dual-gate organic thin film transistors (OTFTs) and PMOS inverters fabricated on 125 µm-thick flexible polyethylene naphthalate (PEN) substrate. All the electrodes (gate, source, and drain) are inkjet-printed, while the parylene dielectric is formed by chemical vapor deposition. A dispenser system is used to print the active channel material using a blend of 2,7-dihexyl-dithieno[2,3-d;2',3'-d']benzo[1,2-b;4,5-b']dithiophene (DTBDT-C6) and polystyrene (PS) in tetralin solvent, which gives highest mobility of 0.43 cm2/Vs. Dual-gate OTFTs are characterized by keeping the other gate electrode either in grounded or floating state. Floating gate electrode devices shows higher apparent mobility and current ratio due to additional capacitance of the parylene dielectric. PMOS inverter circuits are characterized in terms of gain, trip point and noise margin values calculated from the voltage transfer characteristics (VTC). Applied top gate voltage on the load OTFT control the conductivity or threshold voltage (VTh) of the bottom TFT and shift the trip point towards the middle of the VTC curve, and hence increase the noise margin.


2014 ◽  
Vol 15 (2) ◽  
pp. 614-621 ◽  
Author(s):  
M. Benwadih ◽  
A. Aliane ◽  
S. Jacob ◽  
J. Bablet ◽  
R. Coppard ◽  
...  

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