Printed dual-gate organic thin film transistors and PMOS inverters on flexible substrates: Role of top gate electrode

2021 ◽  
Author(s):  
Subhash Singh ◽  
Hiroyuki Matsui ◽  
Shizuo Tokito
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Chemical Vapor ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Polyethylene Naphthalate ◽  
Gate Electrode ◽  
Noise Margin ◽  
Dual Gate

Abstract We report printed single and dual-gate organic thin film transistors (OTFTs) and PMOS inverters fabricated on 125 µm-thick flexible polyethylene naphthalate (PEN) substrate. All the electrodes (gate, source, and drain) are inkjet-printed, while the parylene dielectric is formed by chemical vapor deposition. A dispenser system is used to print the active channel material using a blend of 2,7-dihexyl-dithieno[2,3-d;2',3'-d']benzo[1,2-b;4,5-b']dithiophene (DTBDT-C6) and polystyrene (PS) in tetralin solvent, which gives highest mobility of 0.43 cm2/Vs. Dual-gate OTFTs are characterized by keeping the other gate electrode either in grounded or floating state. Floating gate electrode devices shows higher apparent mobility and current ratio due to additional capacitance of the parylene dielectric. PMOS inverter circuits are characterized in terms of gain, trip point and noise margin values calculated from the voltage transfer characteristics (VTC). Applied top gate voltage on the load OTFT control the conductivity or threshold voltage (VTh) of the bottom TFT and shift the trip point towards the middle of the VTC curve, and hence increase the noise margin.

scholarly journals Double Beneficial Role of Fluorinated Fullerene Dopants on Organic Thin-Film Transistors: Structural Stability and Improved Performance

2020 ◽  
Vol 12 (25) ◽  
pp. 28416-28425 ◽  
Author(s):  
Adara Babuji ◽  
Inés Temiño ◽  
Ana Pérez-Rodríguez ◽  
Olga Solomeshch ◽  
Nir Tessler ◽  
...  
Keyword(s):  
Thin Film ◽  
Structural Stability ◽  
Thin Film Transistors ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Beneficial Role ◽  
Improved Performance

Pentacene Organic Thin-Film Transistors with Dual-Gate Structure

2007 ◽  
Vol 124-126 ◽  
pp. 383-386
Author(s):  
Jae Bon Koo ◽  
Jung Wook Lim ◽  
Chan Hoe Ku ◽  
Sang Chul Lim ◽  
Jung Hun Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Electrostatic Potential ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Gate Structure ◽  
Dual Gate ◽  
Bottom Gate

We report on the fabrication of dual-gate pentacene organic thin-film transistors (OTFTs) using a plasma-enhanced atomic layer deposited (PEALD) 150 nm thick Al2O3 as a bottom gate dielectric and a 300 nm thick parylene or a PEALD 200 nm thick Al2O3 as both a top gate dielectric and a passivation layer. The threshold voltage (Vth) of OTFT with a 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with a PEALD 200 nm thick Al2O3 as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of Vth of OTFT with the dual-gate structure has been successfully understood by an analysis of electrostatic potential.

scholarly journals Charge Carrier Distribution in Low-Voltage Dual-Gate Organic Thin-Film Transistors

2018 ◽  
Vol 8 (8) ◽  
pp. 1341 ◽  
Author(s):  
Rei Shiwaku ◽  
Masataka Tamura ◽  
Hiroyuki Matsui ◽  
Yasunori Takeda ◽  
Tomohide Murase ◽  
...  
Keyword(s):  
Thin Film ◽  
Charge Carrier ◽  
Thin Film Transistors ◽  
High Performance ◽  
Low Voltage ◽  
Organic Thin Film Transistors ◽  
Charge Carrier Density ◽  
Organic Thin Film ◽  
Carrier Distribution ◽  
Dual Gate

Dual-gate organic thin-film transistors (DGOTFTs), which exhibit better electrical properties, in terms of on-current and subthreshold slope than those of single-gate organic thin-film transistors (OTFTs) are promising devices for high-performance and robust organic electronics. Electrical behaviors of high-voltage (>10 V) DGOTFTs have been studied: however, the performance analysis in low-voltage DGOTFTs has not been reported because fabrication of low-voltage DGOTFTs is generally challenging. In this study, we successfully fabricated low-voltage (<5 V) DGOTFTs by employing thin parylene film as gate dielectrics and visualized the charge carrier distributions in low-voltage DGOTFTs by a simulation that is based on finite element method (FEM). The simulation results indicated that the dual-gate system produces a dual-channel and has excellent control of charge carrier density in the organic semiconducting layer, which leads to the better switching characteristics than the single-gate devices.

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