Design and Implementation of a High-Performance and Low-Power Programmable Embedded Weak Signal Processing Platform

2020 ◽  
Author(s):  
Ji Guanni
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Performance ◽  
Weak Signal ◽  
Design And Implementation ◽  
Processing Platform

A Multi-Channel Audio Signal Processing Platform Based on DSP

2011 ◽  
Vol 121-126 ◽  
pp. 1858-1862
Author(s):  
Jie Gao ◽  
Liang Wang ◽  
Jing Min Ma
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Low Power ◽  
Interface Design ◽  
High Performance ◽  
Audio Signal ◽  
Low Power Consumption ◽  
Audio Signal Processing ◽  
Hardware Interface ◽  
Processing Platform

This paper presented a multi-channel audio signal processing platform based on TMS320VC5509A. It introduced the system basic circuit and the hardware interface design of TLV320AIC23B and TMS320VC5509A. The platform can achieve input four-channel signal and output four-channel simultaneously. Due to its low power consumption, high performance and portable feature, the platform has been used in the system of noise reduction headphone.

Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels

2012 ◽  
pp. 278-296
Author(s):  
Dake Liu ◽  
Joar Sohl ◽  
Jian Wang
Keyword(s):  
Signal Processing ◽  
Parallel Programming ◽  
High Performance ◽  
Data Access ◽  
Time Signal ◽  
Hardware System ◽  
Memory Subsystem ◽  
Computing Performance ◽  
Processing Platform ◽  
Parallel Signal Processing

A novel master-multi-SIMD architecture and its kernel (template) based parallel programming flow is introduced as a parallel signal processing platform. The name of the platform is ePUMA (embedded Parallel DSP processor architecture with Unique Memory Access). The essential technology is to separate data accessing kernels from arithmetic computing kernels so that the run-time cost of data access can be minimized by running it in parallel with algorithm computing. The SIMD memory subsystem architecture based on the proposed flow dramatically improves the total computing performance. The hardware system and programming flow introduced in this article will primarily aim at low-power high-performance embedded parallel computing with low silicon cost for communications and similar real-time signal processing.

The Design and Implementation of a Heterogeneous Multi-Core Security Chip Architecture Based on Shared Memory System

2014 ◽  
Vol 668-669 ◽  
pp. 1314-1318
Author(s):  
Lei Zhang ◽  
Ren Ping Dong ◽  
Chang Zhang ◽  
Ya Ping Yu
Keyword(s):  
Low Power ◽  
Computer Architecture ◽  
Shared Memory ◽  
High Performance ◽  
Stream Cipher ◽  
Ic Card ◽  
Task Partitioning ◽  
Core System ◽  
Design And Implementation ◽  
Encryption And Decryption

With the existence of traditional SOC chip, the encryption and decryption speed and low power cannot meet the computing needs of the modern diversity, then we present a heterogeneous multi-core system which designed based on shared memory on the Xilinx Virtex-5 platform. This paper is in-depth research about heterogeneous multi-core password architecture, static task partitioning, scheduling strategy and the communication mechanism between cores. The three cores systems are designed and builded based on shared memory to realize ZUC algorithm which generates a stream cipher on virtex-5 platform. The three microblaze cores are responsible for inter-core communication, the implementation of ZUC algorithm and articulating IC card to read keys. Through the design of three cores system, give full play to the hardware, software and computer architecture parallelism at all levels to improve the performance of the algorithm to achieve high performance green computing.

scholarly journals Analog to Digital Converters (ADC): A Literature Review

2020 ◽  
Vol 184 ◽  
pp. 01025
Author(s):  
Hemlata Dalmia ◽  
Sanjeet K. Sinha
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
Communication Technology ◽  
High Performance ◽  
Reducing Power ◽  
Digital Signal ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Cmos Scaling ◽  
Analog To Digital Conversion

The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

scholarly journals Design and Implementation of 6-Stage 64-bit MIPS Pipelined Architecture

2019 ◽  
Vol 8 (6S2) ◽  
pp. 790-796
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Random Access ◽  
Instruction Set ◽  
Cache Memories ◽  
Design And Implementation ◽  
Pipelined Architecture ◽  
Risc Processor ◽  
High Speed Data

Pipelining is the concept of overlapping of multiple instructions to perform their operations to optimize the time and ability of hardware units. This paper presents the design and implementation of 6 stage pipelined architecture for High performance 64-bit Microprocessor without Interlocked Pipeline Stages (MIPS) based Reduced Instruction set computing (RISC) processor. In this work, combining efforts of pre-fetching unit, forwarding unit, Branch and Jump predicting unit, Hazard unit are used to reduce the hazards. Low power unit is used to minimize the power. Cache Memories, other devices and especially balancing pipeline stages optimize the Speed in this work. DDR4 SDRAM (Double Data Rate type4 Synchronous Dynamic Random Access Memory) controller is employed in this pipeline to achieve high-speed data transfers and to manage the entire system efficiently. Low power, Low delay Flip flops are used in pipeline registers that implicitly enhance the performance of the system. The proposed method provides better results compared to the existing models. The simulation and synthesis results of the proposed Architecture are evaluated by Xilinx 14.7 software and supporting graphs are plotted through MATLAB tool

Algorithm-based low-power and high-performance multimedia signal processing

1998 ◽  
Vol 86 (6) ◽  
pp. 1155-1202 ◽  
Author(s):  
K.J. Ray Liu ◽  
An-Yeu Wu ◽  
A. Raghupathy ◽  
Jie Chen
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Performance ◽  
Multimedia Signal Processing
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