Power Consumption and Radiation Trade-offs in Phased Arrays for 5G Wireless Transport

Author(s):  
Steven Caicedo Mejillones ◽  
Matteo Oldoni ◽  
Stefano Moscato ◽  
Alessandro Fonte ◽  
Michele D'Amico
2011 ◽  
Vol 8 (4) ◽  
pp. 973-990 ◽  
Author(s):  
Feng Xia ◽  
Xue Yang ◽  
Haifeng Liu ◽  
Zhang Da ◽  
Wenhong Zhao

Localization challenges researchers for its contradictive goals, i.e., how to tackle the problem of minimizing energy consumption as well as maintaining localization precision, which are two essential trade-offs in wireless sensor network systems. In this paper, we propose an Energy-Efficient Opportunistic Localization (EEOL) scheme to satisfy the requirement of positional accuracy and power consumption. We explore the idea of opportunistic wakeup probability to wake up an appropriate numbers of sensor nodes, while ensuring the high positional accuracy. Sensor nodes can be triggered by the opportunistic wakeup probability sent from the user. Through utilizing this method, the number of active sensors in the sensing range of the user is decreased, and the power consumption is significantly reduced. Theoretical analysis has been presented to evaluate the performance of EEOL. Simulation results show that EEOL confirms our theoretical analysis.


2010 ◽  
Vol 4 (2) ◽  
Author(s):  
Robert Stone ◽  
FranÃois Gardien ◽  
Antoine Filipe ◽  
Christian Pisella ◽  
Alain Roggi ◽  
...  

Pressure sensors are requisite for many medical implantable devices to monitor physiological pressures or fluid pressure and flow from a subsystem. Size, power consumption, accuracy, sensitivity, stability, and biocompatibility are all key considerations in the design and fabrication of such sensors. Conventional designs, based on piezoresistive technologies, are power consuming with significant drift and temperature error, whereas capacitive solutions are often cumbersome when packaged for biocompatibility. Tronics Microsystems has developed absolute pressure sensors, which achieve the benefits of both technologies. Miniaturization is achieved using a MEMS sensing element and a multifunction ASIC with small form factors. Low power consumption, low drift, high resolution, and waveform capture capability are obtained by using a capacitive MEMS coupled with a sigma-delta, direct capacitance to digital converter. Biocompatibility is achieved with grade II titanium packaging in two form factors (“tubular” or “pancake”) for incorporation into various applications. These sensors have been fabricated, calibrated, and tested extensively over physiologic temperature ranges. The design has achieved power consumption lower than 500 ÂμW at 100 Hz and a drift lower than 0.5% full scale per year. An accuracy of +/−1% full scale, over the temperature range is obtained by on-ASIC nonlinearity and temperature compensation. The two packaging configurations allow analysis of the trade-offs on the temperature range, sensitivity, volume, sterilization, etc. Different feed-through materials permit optimization of the form factors for the tube and the flat sensor and wired or wireless communication.


This is the second chapter of the first section. It presents the mechanical and physical foundations of mobile robots that are needed for a complete understanding of the concepts of further chapters, such as sensor and motion models. It provides a detailed review of the most common electro-mechanical components found in state-of-the-art mobile robots, emphasizing practical aspects, such as weight and size, power consumption, and performance trade-offs. Sensors and actuators, in particular, are stated as the hardware basis for coping with localization and mapping, and thus, specialized sections are devoted to them. The described devices range from low-cost sensors/actuators suitable for hobbyists to expensive professional-grade components.


2005 ◽  
Vol 14 (01) ◽  
pp. 65-98
Author(s):  
S. VANICHAYOBON ◽  
S. K. DHALL ◽  
S. LAKSHMIVARAHAN ◽  
J. K. ANTONIO

Optimizing area and speed in parallel prefix circuits has been considered important for a long time. The issue of power consumption in these circuits, however, has not been addressed. This paper presents a comparative study of different parallel prefix circuits from the point of view of power–speed trade-off. An effective circuit capacitance model that is verified through PSpice simulations is used to investigate the power consumption in parallel prefix circuits. The model results in an analytical function for power consumption for each prefix circuit considered. The degrees of freedom studied include different parallel prefix circuits and voltage scaling. The results of the study were applied to evaluate power–speed trade-offs when different prefix circuits are used in Brent's parallel adder.5


2000 ◽  
Vol 10 (01) ◽  
pp. 19-42 ◽  
Author(s):  
SORIN DRAGHICI

This paper presents a brief review of some analog hardware implementations of neural networks. Several criteria for the classification of general neural networks implementations are discussed and a taxonomy induced by these criteria is presented. The paper also discusses some characteristics of analog implementations as well as some trade-offs and issues identified in the work reviewed. Parameters such as precision, chip area, power consumption, speed and noise susceptibility are discussed in the context of neural implementations. A unified review of various "VLSI friendly" algorithms is also presented. The paper concludes with some conclusions drawn from the analysis of the implementations presented.


2009 ◽  
Vol 18 (04) ◽  
pp. 787-800 ◽  
Author(s):  
SANGHOON KWAK ◽  
JEONG-GUN LEE ◽  
EUN-GU JUNG ◽  
DONGSOO HAR ◽  
MILOS D. ERCEGOVAC ◽  
...  

The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bit-width of each sub-adder. Also the effectiveness of the proposed method was demonstrated by showing the ratio of the power consumption of heterogeneous adder to that of conventional adder.


Author(s):  
Wei Cai ◽  
Cheng Li ◽  
Heng Gu

<p><strong>Objective: </strong>The objective of this research was to design a 2.4 GHz class B Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design.</p><p><strong>Methods: </strong>This paper introduces the design of a 2.4GHz class B power amplifier designed as dual gate topology. This class B power amplifier could transmit 26dBm output power to a 50Ω load. The power added efficiency was 60% minimum and the power gain was 90dB, the total power consumption was 6.9 mW.</p><p><strong>Results:</strong> Besides, accurate device modeling, is needed, due to the leakage and process variations.</p><p><strong>Conclusion</strong>:<strong> </strong>The performance of the power amplifier meets the specification requirements of the desired.</p>


Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6488
Author(s):  
Christia Charilaou ◽  
Spyros Lavdas ◽  
Ala Khalifeh ◽  
Vasos Vassiliou ◽  
Zinon Zinonos

The remarkable evolution of the IoT raised the need for an efficient way to update the device’s firmware. Recently, a new process was released summarizing the steps for firmware updates over the air (FUOTA) on top of the LoRaWAN protocol. The FUOTA process needs to be completed quickly to reduce the systems’ interruption and, at the same time, to update the maximum number of devices with the lowest power consumption. However, as the literature showed, a single gateway cannot optimize the FUOTA procedure and offer the above mentioned goals since various trade-offs arise. In this paper, we conducted extensive experiments via simulation to investigate the impact of multiple gateways during the firmware update process. To achieve that, we extended the FUOTAsim simulation tool to support multiple gateways. The results revealed that several gateways could eliminate the trade-offs that appeared using a single gateway.


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