Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory

A low-power 1Kb phase change random access memory (PCRAM) chip is designed. The chip uses 1T1R (one transistor one resistor) structure and titanium nitride (TiN) bottom electrode (BE) for reducing power consumption. Besides, the write property of the chip is improved by employing a ramp down pulse generator. The chip is fabricated in 130nm CMOS standard technology. The test result shows a 56% power reduction based on TiN BE compared with tungsten (W) BE, which predicts a new direction to realize the commercialization of PCRAM.

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Sub-6F2 Charge Trap Dynamic Random Access Memory Using a Novel Operation Scheme

2006 64th Device Research Conference ◽

10.1109/drc.2006.305173 ◽

2006 ◽

Cited By ~ 1

Author(s):

Zongliang Huo ◽

Seungjae Baik ◽

Shieun Kim ◽

In-seok Yeo ◽

U-in Chung ◽

...

Keyword(s):

Random Access ◽

Random Access Memory ◽

Dynamic Random Access Memory ◽

Access Memory ◽

Charge Trap

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Channel Recessed One Transistor Dynamic Random Access Memory with SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$ Gate Dielectric

Japanese Journal of Applied Physics ◽

10.1143/jjap.51.06fe08 ◽

2012 ◽

Vol 51 ◽

pp. 06FE08

Author(s):

Jin-Kwon Park ◽

Jong-Heon Yang ◽

Won-Ju Cho

Keyword(s):

Gate Dielectric ◽

Random Access ◽

Random Access Memory ◽

Dynamic Random Access Memory ◽

Access Memory

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W as a Bit Line Interconnection in Capacitor-Over-Bit-line (COB) Structured Dynamic Random Access Memory (DRAM) and Feasible Diffusion Barrier Layer

Japanese Journal of Applied Physics ◽

10.1143/jjap.35.1086 ◽

1996 ◽

Vol 35 (Part 1, No. 2B) ◽

pp. 1086-1089 ◽

Cited By ~ 2

Author(s):

Jeong Soo Byun ◽

Jun Ki Kim ◽

Jin Won Park ◽

Jae Jeong Kim

Keyword(s):

Barrier Layer ◽

Diffusion Barrier ◽

Random Access ◽

Random Access Memory ◽

Dynamic Random Access Memory ◽

Access Memory ◽

Diffusion Barrier Layer

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Dielectric Properties of(Pb,La)TiO3Thin Films by Multiple-Cathode Sputtering and Its Application to Dynamic Random Access Memory Capacitors

Japanese Journal of Applied Physics ◽

10.1143/jjap.35.4976 ◽

1996 ◽

Vol 35 (Part 1, No. 9B) ◽

pp. 4976-4979 ◽

Cited By ~ 11

Author(s):

Hiroshi Maiwa ◽

Noboru Ichinose

Keyword(s):

Dielectric Properties ◽

Random Access ◽

Random Access Memory ◽

Dynamic Random Access Memory ◽

Access Memory ◽

Cathode Sputtering

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Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2021.19389 ◽

2021 ◽

Vol 21 (8) ◽

pp. 4216-4222

Author(s):

Songyi Yoo ◽

In-Man Kang ◽

Sung-Jae Cho ◽

Wookyung Sun ◽

Hyungsoon Shin

Keyword(s):

Strong Electric Field ◽

Memory Performance ◽

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Dynamic Random Access Memory ◽

Thin Body ◽

Memory Cells ◽

Access Memory ◽

Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

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