Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

Author(s):  
A. Veloso ◽  
T. Hoffmann ◽  
A. Lauwers ◽  
S. Brus ◽  
J.-F. de Marneffe ◽  
...  
Keyword(s):  
2008 ◽  
Vol 573-574 ◽  
pp. 341-351
Author(s):  
Anne Lauwers ◽  
Jorge Kittl ◽  
Karen Maex

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of nMOS (NiSi) and pMOS (Ni-rich) gates on HfSiON is demonstrated. Linewidth independent phase control with smooth threshold voltage (Vt) roll-off characteristics is achieved for NiSi, Ni2Si and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). A 2-step Ni FUSI process enables simultaneous silicidation of nMOS and pMOS FUSI gates, achieving different Ni/Si ratios on nMOS and pMOS by reduction of the pMOS poly height through a selective and controlled poly etch-back prior to gate silicidation. The RTP1 temperature process window to obtain NiSi or Ni3Si2 at the FUSI/dielectric interface (needed for nMOS devices) is significantly widened for spike anneals as compared to soak anneals. Good overlap between the RTP1 process window for nMOS and pMOS devices is achieved by the reduction of the poly-Si height for pMOS.


Author(s):  
H.H. Rotermund

Chemical reactions at a surface will in most cases show a measurable influence on the work function of the clean surface. This change of the work function δφ can be used to image the local distributions of the investigated reaction,.if one of the reacting partners is adsorbed at the surface in form of islands of sufficient size (Δ>0.2μm). These can than be visualized via a photoemission electron microscope (PEEM). Changes of φ as low as 2 meV give already a change in the total intensity of a PEEM picture. To achieve reasonable contrast for an image several 10 meV of δφ are needed. Dynamic processes as surface diffusion of CO or O on single crystal surfaces as well as reaction / diffusion fronts have been observed in real time and space.


Author(s):  
S. G. Ghonge ◽  
E. Goo ◽  
R. Ramesh ◽  
R. Haakenaasen ◽  
D. K. Fork

Microstructure of epitaxial ferroelectric/conductive oxide heterostructures on LaAIO3(LAO) and Si substrates have been studied by conventional and high resolution transmission electron microscopy. The epitaxial films have a wide range of potential applications in areas such as non-volatile memory devices, electro-optic devices and pyroelectric detectors. For applications such as electro-optic devices the films must be single crystal and for applications such as nonvolatile memory devices and pyroelectric devices single crystal films will enhance the performance of the devices. The ferroelectric films studied are Pb(Zr0.2Ti0.8)O3(PLZT), PbTiO3(PT), BiTiO3(BT) and Pb0.9La0.1(Zr0.2Ti0.8)0.975O3(PLZT).Electrical contact to ferroelectric films is commonly made with metals such as Pt. Metals generally have a large difference in work function compared to the work function of the ferroelectric oxides. This results in a Schottky barrier at the interface and the interfacial space charge is believed to responsible for domain pinning and degradation in the ferroelectric properties resulting in phenomenon such as fatigue.


1994 ◽  
Vol 164 (4) ◽  
pp. 375 ◽  
Author(s):  
B.V. Vasil'ev ◽  
M.I. Kaganov ◽  
V.L. Lyuboshits

2009 ◽  
Vol 129 (6) ◽  
pp. 1169-1175 ◽  
Author(s):  
Michiko Yoshitake ◽  
Shinjiro Yagyu
Keyword(s):  

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.


2020 ◽  
Vol 96 (3s) ◽  
pp. 756-757
Author(s):  
Е.С. Шамин ◽  
Е.Л. Харченко

Данная работа посвящена описанию возможного алгоритма создания моделей резиста с постоянным порогом и расчета окон процесса на их основе. Приведенные изыскания реализованы в виде программного средства, использующего средства моделирования фотолитографии Mentor Graphics Calibre. This work is dedicated to the description of one of possible algorithms of constant threshold resist model generation used for photolithography process window calculation. This algorithm has been realized in the form of a program using Mentor Graphics Calibre modeling tools.


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