A design and implementation of control logic of beam steering unit for phased array radar

Author(s):  
D. Govind Rao ◽  
Yogesh Shakya ◽  
Angela Nalini Margaret ◽  
Abhishek N. Kothari

Phased array radar architecture consists of the multiple antenna elements that are controlled by the active electronic circuits called T/R modules. Transmit/Receive modules (T/R modules) plays vital role in the modern phased array radar system for different radar applications. The problem asserted with electrically scanned phased array radar suffers from two main limitations. First one is the high hardware cost in terms of area and second one is the design complexity. To overcome the above issues, architecture has been developed by implementing single control unit, distributive memory elements and data control logic to design an area efficient control system. The entire system is implemented on Artix-7 FPGA.


Transmit/Receive (T/R) modules plays important role in advanced phased array radar system consists of array of antenna elements. In order to produce beam pattern for multiple radiating elements, the phase angle for each T/R module should be assigned with calculated value. When phase gradient is sent to T/R unit, phase values are calculated for array of elements associated with them. The paper presents a beam steering control system architecture consists of Graphical user interface, group controller with scalable T/R control unit (TRCU) having two hexa decagon T/R module controllers (HTRMCs) and control logic unit for parallel data flow. Calculation of 6 bit phase value from the phase gradient carried out using FPGA. Also, use of logic core and quantization of phase values are discussed. The paper also reports the area factor for the proposed architecture


Sensors ◽  
2021 ◽  
Vol 21 (21) ◽  
pp. 7382
Author(s):  
Yue-Ming Wu ◽  
Hao-Chung Chou ◽  
Cheng-Yung Ke ◽  
Chien-Cheng Wang ◽  
Chien-Te Li ◽  
...  

Phased array technology features rapid and directional scanning and has become a promising approach for remote sensing and wireless communication. In addition, element-level digitization has increased the feasibility of complicated signal processing and simultaneous multi-beamforming processes. However, the high cost and bulky characteristics of beam-steering systems have prevented their extensive application. In this paper, an X-band element-level digital phased array radar utilizing fully integrated complementary metal-oxide-semiconductor (CMOS) transceivers is proposed for achieving a low-cost and compact-size digital beamforming system. An 8–10 GHz transceiver system-on-chip (SoC) fabricated in 65 nm CMOS technology offers baseband filtering, frequency translation, and global clock synchronization through the proposed periodic pulse injection technique. A 16-element subarray module with an SoC integration, antenna-in-package, and tile array configuration achieves digital beamforming, back-end computing, and dc–dc conversion with a size of 317 ×149 × 74.6 mm3. A radar demonstrator with scalable subarray modules simultaneously realizes range sensing and azimuth recognition for pulsed radar configurations. Captured by the suggested software-defined pulsed radar, a complete range–azimuth figure with a 1 km maximum observation range can be displayed within 150 ms under the current implementation.


Author(s):  
D. Govind Rao ◽  
N. S. Murthy ◽  
A. Vengadarajan

This paper deals with the design and implementation of a digital beam former architecture which is developed for 4/8/12/16 element phased array radar. This technique employs a very high performance FPGA to handle large no of parallel complex arithmetic operations including digital down conversion and filtering. A 3MHz echo signal riding on an IF carrier of 60 MHz is under sampled at 50 MHz and down converted digitally to bring the spectrum to echo signal baseband. After suitable decimation filtering, the I and Q channels are multiplied with Recursive Least Squares based optimized complex weights to form partial beams. The prototype architecture employs techniques of pipelining and parallelism to generate multiple beams simultaneously from a 16 element array within 1 μsec. This can be extended to several number of arrays. The critical components employed in this design are eight 16 bit 125 MS/s ADCs and a very high performance state of the art Xilinx FPGA device Virtex-5 FX 130T having several on-chip resources and 150 MHz clock generators.


2020 ◽  
Author(s):  
Zhanling Wang ◽  
Jiapeng Yin ◽  
Chen Pang ◽  
Yongzhen Li ◽  
Xuesong Wang

<div>High cross-polarization isolation (CPI) is crucial to the accurate polarization measurement using polarimetric phased array radar (PPAR). In this paper, we propose an adaptive direction-dependent polarization state configuration (AD2PSC) method to improve the polarization isolation. Compared with conventional fixed polarization state of radiated wave whether it is linear, circular or elliptical polarization state, our AD2PSC approach configures the polarization state on basis of beam steering. To achieve the adaptive configuration of magnitude and phase of the dual-polarization antenna, an improved steepest descent algorithm is put forward. To facilitate the uniform representation for the polarization measurement application of PPAR, the universal expressions of intrinsic and measured backscatter matrices are derived for arbitrary polarization state. The dualpolarization dipole array is used to assess the priority of our proposed method. Compared with the conventional approaches,</div><div>our approach could obtain higher CPI while being available for a larger scanning range. The configured CPI meets the specific polarization requirement for PPAR.</div>


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