C-V Measurement under Different Frequencies and Pulse-mode Voltage Stress to Reveal Shallow and Deep Trap Effects of GaN HEMTs

Author(s):  
Wen Yang ◽  
Jiann-Shiun Yuan ◽  
Balakrishnan Krishnan ◽  
A.J. Tzou ◽  
Wen-Kuan Yeh
2020 ◽  
pp. 1-8
Author(s):  
Jayjit Mukherjee ◽  
Amit Malik ◽  
Seema Vinayak ◽  
D. S. Rawal ◽  
Rajendra S. Dhaka
Keyword(s):  

Author(s):  
M. Wespel ◽  
M. Dammann ◽  
V. Polyakov ◽  
R. Reiner ◽  
P. Waltereit ◽  
...  

Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.


Author(s):  
M. Bouya ◽  
D. Carisetti ◽  
J.C. Clement ◽  
N. Malbert ◽  
N. Labat ◽  
...  

Abstract HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. They are crucial components for the development of base stations in the telecommunications networks and for civil, defense and space radar applications. As well as the improvement of the MMIC performances, the localization of the defects and the failure analysis of these devices are very challenging. To face these challenges, we have developed a complete approach, without degrading the component, based on front side failure analysis by standard (Visible-NIR) and Infrared (range of wavelength: 3-5 µm) electroluminescence techniques. Its complementarities and efficiency have been demonstrated through two case studies.


2018 ◽  
Author(s):  
Oberon Dixon-Luinenburg ◽  
Jordan Fine

Abstract In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.


Sign in / Sign up

Export Citation Format

Share Document