Maximum Resolution of a Probe-Based, Steady-State Thermal Interface Material Characterization Instrument

2016 ◽  
Vol 139 (1) ◽  
Author(s):  
Ronald J. Warzoha ◽  
Andrew N. Smith ◽  
Maurice Harris

Thermal interface materials (TIMs) constitute a critical component for heat dissipation in electronic packaging systems. However, the extent to which a conventional steady-state thermal characterization apparatus can resolve the interfacial thermal resistance across current high-performance interfaces (RT < 1 mm2⋅K/W) is not clear. In this work, we quantify the minimum value of RT that can be measured with this instrument. We find that in order to increase the resolution of the measurement, the thermal resistance through the instrument's reference bars must be minimized relative to RT. This is practically achieved by reducing reference bar length. However, we purport that the minimization of reference bar length is limited by the effects of thermal probe intrusion along the primary measurement pathway. Using numerical simulations, we find that the characteristics of the probes and surrounding filler material can significantly impact the measurement of temperature along each reference bar. Moreover, we find that probes must be spaced 15 diameters apart to maintain a uniform heat flux at the interface, which limits the number of thermal probes that can be used for a given reference bar length. Within practical constraints, the minimum thermal resistance that can be measured with an ideal instrument is found to be 3 mm2⋅K/W. To verify these results, the thermal resistance across an indium heat spring material with an expected thermal contact resistance of ∼1 mm2⋅K/W is experimentally measured and found to differ by more than 100% when compared to manufacturer-reported values.

Author(s):  
Ronald J. Warzoha ◽  
Andrew N. Smith ◽  
Maurice Harris

The performance characteristics of thermal interface materials (TIMs) are quickly outpacing our ability to measure them using steady-state techniques. In fact, scientists have turned to photothermal techniques like Time-domain Thermoreflectance (TDTR) to measure the impedance to heat flow across TIMs, namely due to their relatively low measurement uncertainties. However, such techniques are costly, require significant sample preparation, only measure local thermal impedances and are not yet equipped to measure thermal resistance as a function of pressure. Instead, it is desirable to maximize the resolution of traditional steady-state equipment for these types of measurements. In this work, we develop a more robust and accurate methodology to determine the temperature difference across the junction of a traditional steady-state apparatus using high accuracy measurements of in-situ TIM thickness in tandem with infrared thermography. This methodology eliminates a significant fraction of the uncertainty associated with the measurement of thermal interface resistance. Importantly, the use of this method improves the accuracy of the measurement device by an order of magnitude at interfacial thermal resistance values on the order of 1·10−6m2·K/W when compared to state-of-the-art, thermal probe-based measurement systems.


Author(s):  
Gary L. Solbrekken ◽  
Kazuaki Yazawa ◽  
Avram Bar-Cohen

It is well established that the power dissipation for electronic components is increasing. At the same time, high performance portable equipment with volume, weight, and power limitations are gaining widespread acceptance in the marketplace. The combination of the above conditions requires thermal solutions that are high performance and yet small, light, and power efficient. This paper explores the possibility of using thermoelectric (TE) refrigeration as an integrated solution for portable electronic equipment accounting for heat sink and interface material thermal resistances. The current study shows that TE refrigeration can indeed have a benefit over using just a heat sink. Performance maps illustrating where TE refrigeration offers an advantage over an air-cooled heat sink are created for a parametric range of CPU heat flows, heat sink thermal resistances, and TE material properties. During the course of the study, it was found that setting the TE operating current based on minimizing the CPU temperature (Tj), as opposed to maximizing the amount of heat pumping, significantly reduces Tj. For the baseline case studied, a reduction of 20–30°C was demonstrated over a range of CPU heat dissipation. The parametric studies also illustrate that management of the heat sink thermal resistance appears to be more critical than the CPU/TE interfacial thermal resistance. However, setting the TE current based on a minimum Tj as opposed to maximum heat pumping reduces the system sensitivity to the heat sink thermal resistance.


2014 ◽  
Vol 136 (1) ◽  
Author(s):  
Rui Zhang ◽  
Jian Cai ◽  
Qian Wang ◽  
Jingwei Li ◽  
Yang Hu ◽  
...  

To promote heat dissipation in power electronics, we investigated the thermal conduction performance of Sn-Bi solder paste between two Cu plates. We measured the thermal resistance of Sn-Bi solder paste used as thermal interface material (TIM) by laser flash technique, and a thermal resistance less than 5 mm2 K/W was achieved for the Sn-Bi TIM. The Sn-Bi solder also showed a good reliability in terms of thermal resistance after thermal cycling, indicating that it can be a promising candidate for the TIM used for power electronics applications. In addition, we estimated the contact thermal resistance at the interface between the Sn-Bi solder and the Cu plate with the assistance of scanning acoustic microscopy. The experimental data showed that Sn-Bi solder paste could be a promising adhesive material used to attach power modules especially with a large size on the heat sink.


2013 ◽  
Vol 136 (1) ◽  
Author(s):  
R. Kempers ◽  
A. M. Lyons ◽  
A. J. Robinson

A metal microtextured thermal interface material (MMT-TIM) has been proposed to address some of the shortcomings of conventional TIMs. These materials consist of arrays of small-scale metal features that plastically deform when compressed between mating surfaces, conforming to the surface asperities of the contacting bodies and resulting in a low-thermal resistance assembly. The present work details the development of an accurate thermal model to predict the thermal resistance and effective thermal conductivity of the assembly (including contact and bulk thermal properties) as the MMT-TIMs undergo large plastic deformations. The main challenge of characterizing the thermal contact resistance of these structures was addressed by employing a numerical model to characterize the bulk thermal resistance and estimate the contribution of thermal contact resistance. Furthermore, a correlation that relates electrical and thermal contact resistance for these MMT-TIMs was developed that adequately predicted MMT-TIM properties for several different geometries. A comparison to a commercially available graphite TIM is made as well as suggestions for optimizing future MMT-TIM designs.


Author(s):  
J. C. Matayabas ◽  
Vassou LeBonheur

The recent trend in microprocessor architecture has been to increase the number of transistors (higher power), shrink processor size (smaller die), and increase clock speeds (higher frequency) in order to meet the market demand for high performance microprocessors. These have resulted in the escalation of power dissipation as well as the heat flux at the silicon die level. The Intel packaging technology development group has been challenged to develop packaging solutions that not only meet the package thermal targets but also the reliability requirements. As a result, an integrated heat spreading (IHS) package was developed, comprising a Cu based heat spreader and a first level thermal interface material (TIM) between the die and the heat spreader. Due to CTE mismatches between its different elements, the IHS package is subjected to high level of thermo-mechanical stresses which lead to severe failures post reliability testing. A significant amount of theoretical understanding of thermal resistance has been developed and applied to the development of TIM formulations, and it was found that the thermo-mechanical properties of the TIM material need to be optimized to mitigate the package reliability stresses. Several material and process solutions have been investigated using fundamental approaches, and, as a result of these efforts, low stress silicone gel TIM’s were developed. This paper provides an overview of the silicone gel TIM technologies investigated at Intel, and the key learnings from the fundamental material and package integration studies.


MRS Advances ◽  
2017 ◽  
Vol 2 (58-59) ◽  
pp. 3657-3662
Author(s):  
Qiuhong Zhang ◽  
Levi Elston

Due to the low degree of contact area and weak interfacial adhesion between CNTs and the growth substrate (Cu), large thermal contact resistance is the largest challenge preventing the use of vertically aligned CNTs (VACNTs) as a thermal interface material (TIM). Although significant research has been done regarding the growth of CNTs on reactive substrates by using an appropriate buffer layer in this group’s previous work, there are many unanswered questions associated with using VACNTs as a thermal interface material beyond synthesis. This effort extends prior work on carbon nanotube growth, by concentrating on ways to evaluate/measure CNT-based nanocomposite thermal resistance. In this study, with the use of a laser flash measurement system, the influence of CNT array properties (layer height and density) on the thermal diffusivity and thermal resistance of the CNT composite were investigated. Test results identify a correlation between the CNT array density/thickness and its thermal resistance.


Author(s):  
Hua Bao ◽  
Shirui Luo ◽  
Ming Hu

Thermal transport across material interfaces is crucial for many engineering applications. For example, in microelectronics, small interfacial thermal resistance is desired to achieve efficient heat dissipation. Carbon nanotube (CNT) has extremely high thermal conductivity and can potentially serve as an efficient thermal interface material. However, heat dissipation through CNTs is limited by the large thermal resistance at the CNT-material interface. Here we have proposed a CNT-graphene junction structure to enhance the interfacial thermal transport. Non-equilibrium molecular dynamics simulations have been carried out to show that the thermal conductance can be significantly enhanced by adding a single graphene layer in between CNT and silicon. The mechanism of enhanced thermal transport is attributed to the efficient thermal transport between CNT and graphene and the good contact between graphene and silicon surface.


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