Thermal Resistance Analysis of Sn-Bi Solder Paste Used as Thermal Interface Material for Power Electronics Applications

2014 ◽  
Vol 136 (1) ◽  
Author(s):  
Rui Zhang ◽  
Jian Cai ◽  
Qian Wang ◽  
Jingwei Li ◽  
Yang Hu ◽  
...  

To promote heat dissipation in power electronics, we investigated the thermal conduction performance of Sn-Bi solder paste between two Cu plates. We measured the thermal resistance of Sn-Bi solder paste used as thermal interface material (TIM) by laser flash technique, and a thermal resistance less than 5 mm2 K/W was achieved for the Sn-Bi TIM. The Sn-Bi solder also showed a good reliability in terms of thermal resistance after thermal cycling, indicating that it can be a promising candidate for the TIM used for power electronics applications. In addition, we estimated the contact thermal resistance at the interface between the Sn-Bi solder and the Cu plate with the assistance of scanning acoustic microscopy. The experimental data showed that Sn-Bi solder paste could be a promising adhesive material used to attach power modules especially with a large size on the heat sink.

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 745
Author(s):  
Dongjin Kim ◽  
Yasuyuki Yamamoto ◽  
Shijo Nagao ◽  
Naoki Wakasugi ◽  
Chuantong Chen ◽  
...  

This study introduced the SiC micro-heater chip as a novel thermal evaluation device for next-generation power modules and to evaluate the heat resistant performance of direct bonded copper (DBC) substrate with aluminum nitride (AlN-DBC), aluminum oxide (DBC-Al2O3) and silicon nitride (Si3N4-DBC) ceramics middle layer. The SiC micro-heater chips were structurally sound bonded on the two types of DBC substrates by Ag sinter paste and Au wire was used to interconnect the SiC and DBC substrate. The SiC micro-heater chip power modules were fixed on a water-cooling plate by a thermal interface material (TIM), a steady-state thermal resistance measurement and a power cycling test were successfully conducted. As a result, the thermal resistance of the SiC micro-heater chip power modules on the DBC-Al2O3 substrate at power over 200 W was about twice higher than DBC-Si3N4 and also higher than DBC-AlN. In addition, during the power cycle test, DBC-Al2O3 was stopped after 1000 cycles due to Pt heater pattern line was partially broken induced by the excessive rise in thermal resistance, but DBC-Si3N4 and DBC-AlN specimens were subjected to more than 20,000 cycles and not noticeable physical failure was found in both of the SiC chip and DBC substrates by a x-ray observation. The results indicated that AlN-DBC can be as an optimization substrate for the best heat dissipation/durability in wide band-gap (WBG) power devices. Our results provide an important index for industries demanding higher power and temperature power electronics.


Author(s):  
J. C. Matayabas ◽  
Vassou LeBonheur

The recent trend in microprocessor architecture has been to increase the number of transistors (higher power), shrink processor size (smaller die), and increase clock speeds (higher frequency) in order to meet the market demand for high performance microprocessors. These have resulted in the escalation of power dissipation as well as the heat flux at the silicon die level. The Intel packaging technology development group has been challenged to develop packaging solutions that not only meet the package thermal targets but also the reliability requirements. As a result, an integrated heat spreading (IHS) package was developed, comprising a Cu based heat spreader and a first level thermal interface material (TIM) between the die and the heat spreader. Due to CTE mismatches between its different elements, the IHS package is subjected to high level of thermo-mechanical stresses which lead to severe failures post reliability testing. A significant amount of theoretical understanding of thermal resistance has been developed and applied to the development of TIM formulations, and it was found that the thermo-mechanical properties of the TIM material need to be optimized to mitigate the package reliability stresses. Several material and process solutions have been investigated using fundamental approaches, and, as a result of these efforts, low stress silicone gel TIM’s were developed. This paper provides an overview of the silicone gel TIM technologies investigated at Intel, and the key learnings from the fundamental material and package integration studies.


MRS Advances ◽  
2017 ◽  
Vol 2 (58-59) ◽  
pp. 3657-3662
Author(s):  
Qiuhong Zhang ◽  
Levi Elston

Due to the low degree of contact area and weak interfacial adhesion between CNTs and the growth substrate (Cu), large thermal contact resistance is the largest challenge preventing the use of vertically aligned CNTs (VACNTs) as a thermal interface material (TIM). Although significant research has been done regarding the growth of CNTs on reactive substrates by using an appropriate buffer layer in this group’s previous work, there are many unanswered questions associated with using VACNTs as a thermal interface material beyond synthesis. This effort extends prior work on carbon nanotube growth, by concentrating on ways to evaluate/measure CNT-based nanocomposite thermal resistance. In this study, with the use of a laser flash measurement system, the influence of CNT array properties (layer height and density) on the thermal diffusivity and thermal resistance of the CNT composite were investigated. Test results identify a correlation between the CNT array density/thickness and its thermal resistance.


2016 ◽  
Vol 139 (1) ◽  
Author(s):  
Ronald J. Warzoha ◽  
Andrew N. Smith ◽  
Maurice Harris

Thermal interface materials (TIMs) constitute a critical component for heat dissipation in electronic packaging systems. However, the extent to which a conventional steady-state thermal characterization apparatus can resolve the interfacial thermal resistance across current high-performance interfaces (RT < 1 mm2⋅K/W) is not clear. In this work, we quantify the minimum value of RT that can be measured with this instrument. We find that in order to increase the resolution of the measurement, the thermal resistance through the instrument's reference bars must be minimized relative to RT. This is practically achieved by reducing reference bar length. However, we purport that the minimization of reference bar length is limited by the effects of thermal probe intrusion along the primary measurement pathway. Using numerical simulations, we find that the characteristics of the probes and surrounding filler material can significantly impact the measurement of temperature along each reference bar. Moreover, we find that probes must be spaced 15 diameters apart to maintain a uniform heat flux at the interface, which limits the number of thermal probes that can be used for a given reference bar length. Within practical constraints, the minimum thermal resistance that can be measured with an ideal instrument is found to be 3 mm2⋅K/W. To verify these results, the thermal resistance across an indium heat spring material with an expected thermal contact resistance of ∼1 mm2⋅K/W is experimentally measured and found to differ by more than 100% when compared to manufacturer-reported values.


Author(s):  
Amer M. Hamdan ◽  
Aric R. McLanahan ◽  
Robert F. Richards ◽  
Cecilia D. Richards

This work presents the characterization of a thermal interface material consisting of an array of mercury micro droplets deposited on a silicon die. Three arrays were tested, a 40 × 40 array (1600 grid) and two 20 × 20 arrays (400 grid). All arrays were assembled on a 4 × 4 mm2 silicon die. An experimental facility which measures the thermal resistance across the mercury array under steady state conditions is described. The thermal interface resistance of the arrays was characterized as a function of the applied load. A thermal interface resistance as low as 0.253 mm2 K W−1 was measured. A model to predict the thermal resistance of a liquid-metal micro droplet array was developed and compared to the experimental results. The model predicts the deformation of the droplet array under an applied load and then the geometry of the deformed droplets is used to predict the thermal resistance of the array. The contact resistance of the mercury arrays was estimated based on the experimental and model data. An average contact resistance was estimated to be 0.14 mm2 K W−1.


Author(s):  
David Shaddock ◽  
Stanton Weaver ◽  
Ioannis Chasiotis ◽  
Binoy Shah ◽  
Dalong Zhong

The power density requirements continue to increase and the ability of thermal interface materials has not kept pace. Increasing effective thermal conductivity and reducing bondline thickness reduce thermal resistance. High thermal conductivity materials, such as solders, have been used as thermal interface materials. However, there is a limit to minimum bondline thickness in reducing resistance due to increased fatigue stress. A compliant thermal interface material is proposed that allows for thin solder bondlines using a compliant structure within the bondline to achieve thermal resistance <0.01 cm2C/W. The structure uses an array of nanosprings sandwiched between two plates of materials to match thermal expansion of their respective interface materials (ex. silicon and copper). Thin solder bondlines between these mating surfaces and high thermal conductivity of the nanospring layer results in thermal resistance of 0.01 cm2C/W. The compliance of the nanospring layer is two orders of magnitude more compliant than the solder layers so thermal stresses are carried by the nanosprings rather than the solder layers. The fabrication process and performance testing performed on the material is presented.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000225-000232 ◽  
Author(s):  
Marc Schneider ◽  
Benjamin Leyrer ◽  
Christian Herbold ◽  
Stefan Maikowske

An LED module consisting of 98 UV-LEDs with an emission wavelength of 395 nm placed on a ceramic substrate of 211 mm2 is presented. The module is cooled by a forced air heat sink as well as a high performance microstructured water cooler to lower the thermal resistance. For high thermal conductance a liquid metal as the thermal interface material between substrate and heat sink is used. With the forced air heat sink a maximum irradiance of 27.3 W/cm2 at a forward current of 700 mA and 220 W electrical input power was achieved. The microstructured water cooler enabled an almost doubling of the electrical input power (430 W) while maintaining the chip's maximum temperature. For a reduction of the module's thermal resistance a thick film process for aluminum sheet metal substrates was developed. A prototype LED module with 25 UV-LED chips on an area of 54 mm2 achieved a maximum optical power density of 31.6 W/cm2 at a forward current of 900 mA using a forced air heat sink. For an improved cooling of the LED chips a chip-on-heat sink-technology with embedded water cooling channels is developed to eliminate the thermal interface between substrate and heat sink.


Author(s):  
Douglas DeVoto ◽  
Paul Paret ◽  
Sreekant Narumanchi ◽  
Mark Mihalic

In automotive power electronics packages, conventional thermal interface materials such as greases, gels, and phase change materials pose bottlenecks to heat removal and are also associated with reliability concerns. There is an industry trend towards high thermal performance bonded interfaces. However, due to coefficient of thermal expansion mismatches between materials/layers and resultant thermomechanical stresses, adhesive and cohesive fractures could occur, posing a problem from a reliability standpoint. These defects manifest themselves in increased thermal resistance in the package. The objective of this research is to investigate and improve the thermal performance and reliability of emerging bonded interface materials for power electronics packaging applications. We present results for thermal performance and reliability of bonded interfaces based on thermoplastic (polyamide) adhesive, with embedded near-vertical aligned carbon fibers, as well as sintered silver material. The results for these two materials are compared to conventional lead-based (Sn63Pb37) bonded interfaces. These materials were bonded between 50.8-mm × 50.8-mm cross-sectional footprint silicon nitride substrates and copper base plate samples. Samples of the substrate/base plate bonded assembly underwent thermal cycling from −40°C to 150°C according to Joint Electron Devices Engineering Council standard Number 22-A104D for up to 2,000 cycles. The dwell time of the cycle was 10 minutes and the ramp rate was 5°C/minute. Damage was monitored every 100 cycles by acoustic microscopy as an indicator of an increase in thermal resistance of the interface layer. The acoustic microscopic images of the bonded interfaces after 2,000 thermal cycles showed that thermoplastics with embedded carbon fibers performed quite well with no defects, whereas interface delamination occurred in the case of sintered silver material. Both these materials showed a superior bond quality as compared to the lead-based solder interface even after 1,000 thermal cycles.


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