FPGA Implementation of a Soft Sensor for the Estimation of the Freezing Point of Kerosene

2009 ◽  
Author(s):  
Riccardo Caponetto ◽  
Giovanni Dongola ◽  
Antonio Gallo ◽  
Maria Gabriella Xibilia
Keyword(s):  
Neural Networks ◽  
Field Programmable Gate Array ◽  
Freezing Point ◽  
Industrial Process ◽  
Soft Sensor ◽  
Fpga Implementation ◽  
Distillation Unit ◽  
Atmospheric Distillation ◽  
New Strategy ◽  
Field Programmable

A new strategy to realize an FPGA implementation of a soft sensor for an industrial process is proposed. The proposed approach is based on the integration on Field Programmable Gate Array (FPGA) of a neural networks. The proposed method has been applied to develop a soft sensor for the estimation of the freezing point of kerosene in an atmospheric distillation unit (topping) working in a refinery in Sicily, Italy.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

Memristor Oscillators and its FPGA Implementation

2011 ◽  
Vol 383-390 ◽  
pp. 6992-6997 ◽  
Author(s):  
Ai Xue Qi ◽  
Cheng Liang Zhang ◽  
Guang Yi Wang
Keyword(s):  
Numerical Simulation ◽  
Chaotic System ◽  
Field Programmable Gate Array ◽  
Chaotic Attractor ◽  
Hardware Implementation ◽  
Fpga Implementation ◽  
Experimental Results ◽  
Linear Resistance ◽  
Non Linear ◽  
Field Programmable

This paper presents a method that utilizes a memristor to replace the non-linear resistance of typical Chua’s circuit for constructing a chaotic system. The improved circuit is numerically simulated in the MATLAB condition, and its hardware implementation is designed using field programmable gate array (FPGA). Comparing the experimental results with the numerical simulation, the two are the very same, and be able to generate chaotic attractor.

scholarly journals Design and Implementation of Perceptron Neuron in Machine Learning for Handwritten Character Recognition

2020 ◽  
Vol 9 (10) ◽  
pp. 357-363
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Feature Extraction ◽  
Field Programmable Gate Arrays ◽  
Fpga Implementation ◽  
Floating Point ◽  
Neuron Network ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Due to the exponential increase of electronic devices that are connected to the Internet, the amount of data that they produce have grown to the same extent. In order to face the processing of these data, the use of some automatic learning algorithms, also known as Machine Learning, has become widespread. The most popular is the one known as neural networks. These algorithms need a great deal of resources to compute all their operations, and because of that, they have been traditionally implemented in application specific integrated circuits. However, recently there have been a boom in implementations in field programmable gate arrays, also known as FPGAs. These allow greater parallelism in the implementation of the algorithms. Field Programmable Gate Arrays (FPGA) implementation based feature extraction method is proposed in this paper. This particular application is handwritten offline digit recognition. The classification depends on simple 2 layer MultiLayer Perceptron (MLP). The particular feature extraction approach is suitable for execution of FPGA because it is utilized with subtraction and addition operations. From Standard database handwritten digit images of normalized 40×40 pixel the features are extracted by the proposed method. It has been discovered by experiential outcomes that 85% accuracy is achieved by proposed system. Overall, as compared to other systems, it is less complex, more accurate and simple. Further this project explains IEE-754 format single precision floating point MAC unit’s FPGA implementation which is utilized for feeding the neurons weighted inputs in artificial neural networks. Data representation range is improved by floating point numbers utilization to a higher number from smaller number that is highly suggested for Artificial Neuron Network. The code is developed in HDL, simulated and synthesis results are extracted using Xilinx synthesis tools .In order to validate its computational accuracy of the FFT, an MATLAB validation script is used to verify the output of HDL with standard reference model.

A Real-Time Deep Learning OFDM Receiver

2022 ◽  
Vol 15 (3) ◽  
pp. 1-25
Author(s):  
Stefan Brennsteiner ◽  
Tughrul Arslan ◽  
John Thompson ◽  
Andrew McCormick
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Orthogonal Frequency Division Multiplexing ◽  
Frequency Division Multiplexing ◽  
Frequency Division ◽  
Field Programmable ◽  
Gate Array ◽  
Fully Connected

Machine learning in the physical layer of communication systems holds the potential to improve performance and simplify design methodology. Many algorithms have been proposed; however, the model complexity is often unfeasible for real-time deployment. The real-time processing capability of these systems has not been proven yet. In this work, we propose a novel, less complex, fully connected neural network to perform channel estimation and signal detection in an orthogonal frequency division multiplexing system. The memory requirement, which is often the bottleneck for fully connected neural networks, is reduced by ≈ 27 times by applying known compression techniques in a three-step training process. Extensive experiments were performed for pruning and quantizing the weights of the neural network detector. Additionally, Huffman encoding was used on the weights to further reduce memory requirements. Based on this approach, we propose the first field-programmable gate array based, real-time capable neural network accelerator, specifically designed to accelerate the orthogonal frequency division multiplexing detector workload. The accelerator is synthesized for a Xilinx RFSoC field-programmable gate array, uses small-batch processing to increase throughput, efficiently supports branching neural networks, and implements superscalar Huffman decoders.

scholarly journals Hyperchaotic Chameleon: Fractional Order FPGA Implementation

Complexity ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-16 ◽  
Author(s):  
Karthikeyan Rajagopal ◽  
Anitha Karthikeyan ◽  
Prakash Duraisamy
Keyword(s):  
Resource Utilization ◽  
Fractional Order ◽  
Field Programmable Gate Array ◽  
Dynamic Properties ◽  
Fpga Implementation ◽  
Hyperchaotic System ◽  
Hidden Attractor ◽  
Hidden Attractors ◽  
Field Programmable ◽  
Fractional Orders

There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their relationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden attractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated. Fractional order models of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable gate array (FPGA) implementations of the systems with their power and resource utilization are presented.

scholarly journals InSight: An FPGA-Based Neuromorphic Computing System for Deep Neural Networks

2020 ◽  
Vol 10 (4) ◽  
pp. 36
Author(s):  
Taeyang Hong ◽  
Yongshin Kang ◽  
Jaeyong Chung
Keyword(s):  
Neural Networks ◽  
Image Classification ◽  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
Deep Neural Networks ◽  
Computing System ◽  
Neuromorphic Computing ◽  
Neuromorphic Hardware ◽  
Field Programmable ◽  
Gate Array

Deep neural networks have demonstrated impressive results in various cognitive tasks such as object detection and image classification. This paper describes a neuromorphic computing system that is designed from the ground up for energy-efficient evaluation of deep neural networks. The computing system consists of a non-conventional compiler, a neuromorphic hardware architecture, and a space-efficient microarchitecture that leverages existing integrated circuit design methodologies. The compiler takes a trained, feedforward network as input, compresses the weights linearly, and generates a time delay neural network reducing the number of connections significantly. The connections and units in the simplified network are mapped to silicon synapses and neurons. We demonstrate an implementation of the neuromorphic computing system based on a field-programmable gate array that performs image classification on the hand-wirtten 0 to 9 digits MNIST dataset with 99.37% accuracy consuming only 93uJ per image. For image classification on the colour images in 10 classes CIFAR-10 dataset, it achieves 83.43% accuracy at more than 11× higher energy-efficiency compared to a recent field-programmable gate array (FPGA)-based accelerator.

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