Performances of a High-Speed Impedance Camera for Flow Informatics

Volume 1 ◽  
2004 ◽  
Author(s):  
Y. Ma ◽  
M. Wang
Keyword(s):  
Image Reconstruction ◽  
Flow Velocity ◽  
Cross Sections ◽  
Digital Signal Processor ◽  
High Speed ◽  
Cross Correlation ◽  
Correlation Method ◽  
Digital Signal ◽  
Two Phase ◽  
Impedance Contrast

An impedance camera has been developed and optimized for visualization and measurement of two-phase flows. This camera, in its basic construction, can synchronously map two cross sections of a pipeline flow in time sequence, where the components of the flow have impedance contrast. Flow velocity distribution can be implemented from the two series of images using the cross-correlation method. The data capture, image reconstruction, concentration and velocity implementation, all are processed on-line using multi-digital signal processor built in the camera. This paper presents a part of test results regarding to the system major performances of the measurement repeatability, consistency of 16 parallel measurement channels, speeds of data acquisition, rate of image reconstruction and cross-correlation implementation, estimation of the discrimination error in flow velocity and flow rate measurements, etc.

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

2000 ◽  
Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras
Keyword(s):  
Cross Sections ◽  
Digital Signal Processor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Digital Signal ◽  
Yield Enhancement ◽  
Final Conclusion ◽  
Stage Separation ◽  
Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

The Research on Phantom-Bit Technology of Digital Phase Shifters for Satellite Tracking System of Phase Array

2014 ◽  
Vol 644-650 ◽  
pp. 4555-4558
Author(s):  
Chao Hai Li ◽  
Wen Xian Jiang ◽  
Guo Long Wang
Keyword(s):  
High Speed ◽  
Phased Array ◽  
Tracking System ◽  
Correlation Method ◽  
Digital Signal ◽  
Satellite Tracking ◽  
Phase Shifters ◽  
Phase Array ◽  
Satellite Platform ◽  
Beam Displacement

Phased array satellite platform self-tracking system is for the stability between the missiles and other high-speed movement of the platform and the relay satellite two-way information transmission needs to carry out the self-tracking technology research of onboard platform-dimensional active phased array satellite. The system uses a sub-array correlation method for accurate measurement of the angle of the satellite signal. Receiving array is divided into four 4 * 4 sub-array, each antenna signal combining unit 4 sub array for 4-way A / D to be converted, through down-conversion, filtering, extraction and other processes to get a digital baseband signal, the baseband digital signal processing is to extract the angle error information into digital beam orientation system for tracking filtering operation, thereby ensuring that the transceiver has been aligned with the satellite antenna beam direction. In this paper ,phantom-bit technology for satellite tracking system under the condition of minimum beam displacement is researched for satellite tracking system.

scholarly journals Detection and control of a gyroscopically induced vibration to improve the balance of a single-wheel robot

2017 ◽  
Vol 37 (3) ◽  
pp. 443-455 ◽  
Author(s):  
Sangdeok Lee ◽  
Seul Jung
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Balance Control ◽  
A Priori ◽  
Experimental Studies ◽  
Notch Filter ◽  
Digital Signal ◽  
Control Performance ◽  
And Control ◽  
Balancing Control

In this article, an experimental investigation of the detection of a gyroscopically induced vibration and the balancing control performance of a single-wheel robot is presented. The balance of the single-wheel robot was intended to be maintained by virtue of the gyroscopic effect induced from a highly rotating flywheel. Since the flywheel rotates at a high speed, an asymmetrical structure of a flywheel causes an irregular rotation and becomes one of the major vibration sources. A vibration was detected and suppressed a priori before applying control algorithms to the robot. Gyroscopically induced vibrations can empirically be detected with different rotational velocities. The detection of the balancing angle of the single-wheel robot was accomplished by using an attitude and heading reference system. After identifying the vibrating frequencies, a notch filter was designed to suppress the vibration at the typical frequencies identified through experiments. A digital filter was designed and implemented in a digital signal processor(DSP) along with the control scheme for the balance control performance. The performance of the proposed method was verified by the experimental studies on the balancing control of the single-wheel robot. Experimental results confirmed that the notch filter designed following the detection of the flywheel’s vibration actually improved the balancing control performance. A half of the vibration magnitude was reduced by the proposal.

A Polarization Stabilization Control System Based on DSP

2014 ◽  
Vol 631-632 ◽  
pp. 806-810 ◽  
Author(s):  
Qing Xiang Hou ◽  
Xue Guang Yuan ◽  
Yan Gan Zhang ◽  
Jin Nan Zhang
Keyword(s):  
Control System ◽  
Digital Signal Processor ◽  
High Speed ◽  
Particle Swarm Optimization Algorithm ◽  
Low Frequency ◽  
Digital Signal ◽  
Rf Power ◽  
Swarm Optimization ◽  
Modified Particle Swarm Optimization ◽  
Stabilization Control

A polarization stabilization control system based on digital signal processor (DSP) is proposed in this paper. The system uses low frequency radio frequency (RF) power as control signal for polarization stabilization, and it does not need high-speed circuit to track fast polarization change. Modified particle swarm optimization algorithm is utilized and the effectiveness of polarization stabilization control is experimentally verified.

scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

Low Power, High Speed and Area Efficient Binary Count Multiplier

2016 ◽  
Vol 25 (04) ◽  
pp. 1650027 ◽  
Author(s):  
Kore Sagar Dattatraya ◽  
Belgudri Ritesh Appasaheb ◽  
Ramdas Bhanudas Khaladkar ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Digital Signal Processor ◽  
Word Length ◽  
High Speed ◽  
Digital Signal ◽  
General Purpose ◽  
Computation Method ◽  
Partial Product ◽  
Wallace Tree ◽  
Power Delay Product ◽  
Binary Count

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

Design and Implementation of Audio Process System Based on DSP

2014 ◽  
Vol 945-949 ◽  
pp. 1752-1755
Author(s):  
Chui Xin Chen ◽  
Yang Hong Mao
Keyword(s):  
Real Time ◽  
Digital Signal Processor ◽  
High Speed ◽  
Audio Signal ◽  
Reference Value ◽  
Digital Signal ◽  
Real Time Processing ◽  
Audio Processing ◽  
Time Processing ◽  
Process System

The real-time processing for the input analog audio signal, audio processing program is proposed based on DSP. The system use FFT algorithm as the core, first, the input analog audio signal is sampled and A/D conversion using TLV320AIC23, and then use high speed digital signal processor to make real-time processing for the signal. Theoretical and experimental results show that the system can meet the design requirements, it has the advantage of high real-time and simple structure. The system has a good application and reference value for the development and design of data collecting and remote monitoring.

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