Effective Thermal Conductivity of Six Sigma’s Copper Reinforced Column Grid Array Interconnect for Ceramic Microelectronic Packages

Author(s):  
Mark Eblen

Thermal management of flip chip style integrated circuits often relies on thermal conduction through the ceramic package and high lead solder grid array leads into the printed wiring board as the primary path for heat removal. Thermal analysis of this package configuration requires accurate characterization of the sometimes geometrically complex package-to-board interface. Given the unique structure of the Six Sigma column grid array (CGA) interconnect, a detailed finite element submodel was used to numerically derive the effective thermal conductivity with comparisons to a conventional CGA interconnect. Once an effective thermal conductivity value is obtained, the entire interconnect layer can be represented as a fictitious cuboid layer for inclusion in a more traditional “closed-form” thermal resistance calculation. This method allows the package designer a quick and robust method to evaluate initial thermal design study tradeoffs.

2017 ◽  
Vol 27 (11) ◽  
pp. 2433-2450 ◽  
Author(s):  
Eric Monier-Vinard ◽  
Brice Rogie ◽  
Valentin Bissuel ◽  
Najib Laraqi ◽  
Olivier Daniel ◽  
...  

Purpose Latest Computational Fluid Dynamics (CFDs) tools allow modeling more finely the conjugate thermo-fluidic behavior of a single electronic component mounted on a Printed Wiring Board (PWB). A realistic three-dimensional representation of a large set of electric copper traces of its composite structure is henceforth achievable. The purpose of this study is to confront the predictions of the fully detailed numerical model of an electronic board to a set of experiment results to assess their relevance. Design/methodology/approach The present study focuses on the case of a Ball Grid Array (BGA) package of 208 solder balls that connect the component electronic chip to the Printed Wiring Board. Its complete geometrical definition has to be coupled with a realistic board layers layout and a fine description of their numerous copper traces to appropriately predict the way the heat is spread throughout that multi-layer composite structure. The numerical model computations were conducted on four CFD software then compare to experiment results. The component thermal metrics for single-chip packages are based on the standard promoted by the Joint Electron Device Engineering Council (JEDEC), named JESD-51. The agreement of the numerical predictions and measurements has been done for free and forced convection. Findings The present work shows that the numerical model error is lower than 2 per cent for various convective boundary conditions. Moreover, the establishment of realistic numerical models of electronic components permits to properly apprehend multi-physics design issues, such as joule heating effect in copper traces. Moreover, the practical modeling assumptions, such as effective thermal conductivity calculation, used since decades, for characterizing the thermal performances of an electronic component were tested and appeared to be tricky. A new approach based on an effective thermal conductivity matrix is investigated to reduce computation time. The obtained numerical results highlight a good agreement with experimental data. Research limitations/implications The study highlights that the board three-dimensional modeling is mandatory to properly match the set of experiment results. The conventional approach based on a single homogenous layer using effective thermal conductivity calculation has to be banned. Practical implications The thermal design of complex electronic components is henceforth under increasing control. For instance, the impact of gold wire-bonds can now be investigated. The three-dimensional geometry of sophisticated packages, such as in BGA family, can be imported with all its internal details as well as those of its associated test board to build a realistic numerical model. The establishment of behavioral models such as DELPHI Compact Thermal Models can be performed on a consistent three-dimensional representation with the aim to minimize computation time. Originality/value The study highlights that multi-layer copper trace plane discretization could be used to strongly reduce computation time while conserving a high accuracy level.


Author(s):  
H.W. Ho ◽  
J.C.H. Phang ◽  
A. Altes ◽  
L.J. Balk

Abstract In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.


1993 ◽  
Vol 115 (4) ◽  
pp. 366-372 ◽  
Author(s):  
G. G. Stefani ◽  
N. S. Goel ◽  
D. B. Jenks

Thermal modeling of Surface Mount Technology (SMT) microelectronics packages is difficult due to the complexity of the printed wiring board (PWB) plates through hole (PTH) structure. A simple, yet powerful finite difference based approach, called EPIC (Equivalent Parameter for Interfacial Cells), for modelling complex 2-D and 3-D geometries with multiple materials is used to model the PTH structure. A technique for computing an effective thermal conductivity for the PWB is presented. The results compare favorably with those from a commercially available finite element package but require far less computer time.


Author(s):  
Yasushi Koito ◽  
Toshio Tomimura ◽  
Shuichi Torii

This paper addresses the methodology to estimate the effective thermal conductivity of the wiring board, where the metal wiring network is very complicated and then the thermal conductivity of the metal wiring is more than 1000 times higher than that of the resign board. Based on the concept of analogy between the electric and the thermal resistance network, two types of estimation equations are derived by dividing the composite system parallel or perpendicular to the heated/cooled surface. When the ratio of higher to lower thermal conductivities is less than 10, the estimated values by these equations agree with each other. However, the difference is clearly found between them when the ratio is larger than 100. The estimated values are moreover compared with the exact solutions, which are obtained by numerical simulation of heat transfer using Microsoft Excel, and then the applicability of the present estimation methodology is discussed. It is found that the thermal resistance network obtained by dividing the composite system perpendicular to the heated/cooled surface is effective to estimate the effective thermal conductivity of the composite system.


2000 ◽  
Author(s):  
V. H. Adams ◽  
V. A. Chiriac ◽  
T.-Y. Tom Lee

Abstract Computational Fluid Dynamics (CFD) simulations were conducted to characterize the thermal performance of Molded Array Plastic Ball Grid Array (MAP PBGA) packages for hand-held applications. Due to size constraints, these PBGA packages tend to have fine pitch solder ball arrays and small overall size. Thermal analysis is required to assess the design risks associated with this trend toward smaller size and increasing power dissipation requirements. A conjugate heat transfer problem, in which radiative losses from the exposed surfaces of the package and the printed wiring board to the walls of the wind tunnel, was solved for horizontal natural convection cooling conditions. Thermal model assumptions and development for the MAP PBGA package are provided. The model is benchmarked with measurements obtained for a 64 I/O 0.8 mm pitch, 8 mm MAP PBGA. Predictions for junction-to-ambient thermal resistance were within 10% of measured values. Baseline simulations were conducted for 0.8 mm pitch MAP PBGA packages with substrate/die size combinations in the range of 6 to 12 mm substrate size and 3.81 to 7.62 mm die size. Junction-to-ambient thermal resistances varied over the range of 28.8 °C/W to 62.4 °C/W. Methods to improve thermal performance of these packages were investigated. Previous work indicated that effective conduction to the substrate by heat spreaders, metallic lids, mold compound, heat sinks, and their combinations promoted thermal performance. A necessary further step is to understand how effective area for heat spreading inside the package affects its thermal behavior, while varying the die size for package configurations with and without heat spreader. Studies were conducted to evaluate thermal performance improvement through the use of a copper heat spreader on the package top surface as it is affected by die size, package size, and substrate effective thermal conductivity. Substrate effective thermal conductivity is varied through the use of two and four layer substrates with thermal vias under the die. Results show a modest 1% to 15% reduction in junction-to-ambient thermal resistance for the MAP PBGA package sizes of interest.


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