High Reliability Flip Chip Using Low CTE Laminate Substrates

2005 ◽  
Author(s):  
D. Scott Copeland ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Guoyun Tian ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Carbon Fiber ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Experimental Testing ◽  
High Reliability ◽  
Low Cost ◽  
Substrate Material ◽  
Space Applications ◽  
Sandwich Construction ◽  
Test Chips

In this work, we report on our efforts to develop high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. −55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR®). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.

Damage and Failures of CGA/BGA Assemblies Under Thermal Cycling and Dynamic Loadings

2013 ◽  
Author(s):  
Reza Ghaffarian
Keyword(s):  
Thermal Cycling ◽  
Mechanical Loading ◽  
Test Data ◽  
Printed Circuit Board ◽  
High Reliability ◽  
Circuit Board ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Space Applications ◽  
High Processing

Commercial-off-the-shelf column/ball grid array packaging (COTS CGA/BGA) technologies in high-reliability versions are now being considered for use in high-reliability electronic systems. For space applications, these packages are prone to early failure due to the severe thermal cycling in ground testing and during flight, mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of solder interconnections decreases, susceptibility to thermal, mechanical loading and cycling fatigue grows even more. This paper reviews technology as well as thermo-mechanical reliability of field programmable gate array (FPGA) IC packaging developed to meet demands of high processing powers. The FPGAs that generally come in CGA/PBGA packages now have more than thousands of solder balls/columns under the package area. These packages need not only to be correctly joined onto printed circuit board (PCB) for interfacing; they also should show adequate system reliability for meeting thermo-mechanical requirements of the electronics hardware application. Such reliability test data are rare or none for harsher environmental applications, especially for CGAs having more than a thousand of columns. The paper also presents significant test data gathered under thermal cycling and drop testing for high I/O PBGA/CGA packages assembled onto PCBs. Damage and failures of these assemblies after environmental exposures are presented in detail. Understanding the key design parameters and failure mechanisms under thermal and mechanical conditions is critical to developing an approach that will minimize future failures and will enable low-risk insertion of these advanced electronic packages with high processing power and in-field re-programming capability.

Reliability of Ceramic Column Grid Array (CCGA717) Interconnect Packages Under Extreme Temperatures for Space Applications*

2010 ◽  
Vol 7 (1) ◽  
pp. 16-24 ◽  
Author(s):  
Rajeshuni Ramesham
Keyword(s):  
Thermal Cycling ◽  
Experimental Test ◽  
High Reliability ◽  
Extreme Temperature ◽  
Electrical Performance ◽  
Extreme Temperatures ◽  
Thermal Cycles ◽  
Space Applications ◽  
Temperature Range

Ceramic column grid array packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performance, compatibility with standard surface-mount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, flight avionics, and payload electronics. As these packages tend to have less solder joint strain relief than leaded packages, the reliability of CCGA packages is very important for short-term and long-term space missions. CCGA interconnect electronic package printed wiring boards (PWBs) of polyimide have been assembled, inspected nondestructively, and subsequently subjected to extreme temperature thermal cycling to assess the reliability for future deep space, short- and long-term, extreme temperature missions. In this investigation, the employed temperature range covers from −185°C to +125°C extreme thermal environments. The test hardware consists of two CCGA717 packages with each package divided into four daisy-chained sections, for a total of eight daisy chains to be monitored. The CCGA717 package is 33 mm × 33 mm with a 27 × 27 array of 80%/20% Pb/Sn columns on a 1.27 mm pitch. The resistance of daisy-chained, CCGA interconnects was continuously monitored as a function of thermal cycling. Electrical resistance measurements as a function of thermal cycling are reported and the tests to date have shown significant change in daisy chain resistance as a function of thermal cycling. The change in interconnect resistance becomes more noticeable as the number of thermal cycles increases. This paper will describe the experimental test results of CCGA testing under extreme temperatures. Standard Weibull analysis tools were used to extract the Weibull parameters to understand the CCGA failures. Optical inspection results clearly indicate that the solder joints of columns with the board and the ceramic package have failed as a function of thermal cycling. The first failure was observed at the 137th thermal cycle and 63.2% failures of daisy chains have occurred by about 664 thermal cycles. The shape parameter extracted from the Weibull plot was about 1.47, which indicates the failures were related to failures that occurred during the flat region or useful life region of the standard bathtub curve. Based on this experimental test data, one can use the CCGAs for the temperature range studied for ∼100 thermal cycles (ΔT = 310°C, 5°C/minute, and 15 min dwell) with a high degree of confidence for high reliability space and other applications.

Flip chip reliability and design rules for SIP module

2017 ◽  
Vol 2017 (1) ◽  
pp. 000754-000760 ◽  
Author(s):  
Adrien Morard ◽  
Jean-Christophe Riou ◽  
Gabriel Pares
Keyword(s):  
Flip Chip ◽  
High Reliability ◽  
Signal Transmission ◽  
3D Models ◽  
Organic Substrate ◽  
Bottom Surface ◽  
Active Components ◽  
Design Rules ◽  
3D Architecture ◽  
Test Chips

Abstract The first part of this work is dedicated to the study of “system in package” (SiP) solutions based on different substrates, namely organic or silicon. Generally speaking a SIP is composed by several active and passive components stacked on an interposer. Benchmarks done by Safran have demonstrated that in terms of substrate, embedded die technology leads to several advantages compared to 3D TSV or TGV based packaging approaches. The benefits leaded by this substrate is the possibility to embed some Surface Mount Technologies, bare chips or integrated passives devices (IPD) banks directly above or below the stacked active components. This way, top and bottom surface of the substrate can be used to integrate several heterogeneous dies side by side while using low profile flip-chip assemblies on the C4 side. Finally, in this kind of 3D architecture, this embedded technology enable a gain of integration, without using costly TSV connections. Substrates of high quality allow a reduction of interconnection pitches leading to very aggressive integration. Secondly, a 3D stack with 3 levels of components, as described above, means to, at least, 2 or 3 REACH compliant sequential assembly processes, depending on the needs. In order to consider all the solutions for an optimized integration and a high reliability, this work focused on the study of a simple SIP, which includes the top die assembled by flip-chip. For the flip chip hybridization, copper-pillars technologies are studied in the case of both organic and silicon interposers. The aim of this study is to understand in depth both processes and to obtain information on the reliability aspect after thermal cycling stress of the flip chip assembly. Thirdly, we built many silicon test chips with different characteristics with a dedicated daisy chain test vehicle. The different parameters are: chips' thicknesses (50 to 200 μm), chips' sizes (2 to 8 mm), bump structures (diameter), and the pitches of the interconnection (from 50 to 250 μm) and the number of interconnection rows. Designs were chosen in order to fit real operational configurations. Moreover, these configurations are interesting to build a comprehensive model in order to understand the failure mechanisms. These chips are then stacked by flip-chip on the silicon and on the organic substrate. We are also designing the two configurations of substrates. Only the production of the organics part is outsourced. Fourth, with all these configurations we will be able to fit the thermo-cycling test results with thermos-mechanical simulations done by finite elements. 3D models will take into account the different geometries in order to understand and quantify the various key parameters. The analysis will mainly focus on 3D interconnections. Design rules based on the results will be derivate. The aim is to obtain dimensional criteria based on stress versus deformation responses. Information obtained will be exploited for designing the future functional SIP. Fifth, in order to assess the electrical behaviors of this 3D architecture, signal integrity aspect will be considered as well. As for the design, the migration from an existing 2D electrical design to a 3D architecture design will be studied keeping the signal transmission without any degradation. The ultimate aim of this work is to define mechanical and electrical design rules that can then be used in functional SiP modules.

Die Stress Variation During Thermal Cycling Reliability Tests

2007 ◽  
Author(s):  
M. Kaysar Rahim ◽  
Jordan Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Thermal Cycling ◽  
Electronic Packaging ◽  
Room Temperature ◽  
Flip Chip ◽  
Constitutive Relations ◽  
Temperature Cycling ◽  
Material Behavior ◽  
Aging Effects ◽  
Test Chips

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 × 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

Characterization of Die Stress Distributions in Area Array Flip Chip Packaging

2009 ◽  
Author(s):  
Jordan Roberts ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Power ◽  
Temperature Cycling ◽  
Aging Effects ◽  
Area Array ◽  
Power Cycling ◽  
Die Stress ◽  
On Chip ◽  
Test Chips

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during thermal cycling and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach also allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, initial experiments have been performed to analyze the effects of thermal cycling and power cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). Power cycling of selected parts was performed by exciting the on-chip heaters on the test chips with power levels typical of microprocessor die. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show some cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of temperature cycling duration are currently being correlated with the delaminations occurring at the interfaces between the die and underfill and the die and lid adhesive. In addition, finite element models of the packages are being developed and correlated with the data.

Reliability of Anisotropically Conductive Adhesive Joints on a Flip-Chip/FR-4 Substrate

2002 ◽  
Vol 124 (3) ◽  
pp. 240-245 ◽  
Author(s):  
Johan Liu ◽  
Zonghe Lai
Keyword(s):  
Flip Chip ◽  
High Reliability ◽  
Low Cost ◽  
Adhesive Joints ◽  
Temperature Cycling ◽  
Conductive Adhesive ◽  
Resistance Measurement ◽  
Time To Failure ◽  
Low Cost Substrate

A reliability study on anisotropically conductive adhesive joints on a Flip-Chip/FR-4 assembly has been carried out. In the study, nine types of anisotropic conductive adhesive (ACA) and one nonconductive film (NCF) were used. In total, nearly one-thousand single joints were subjected to reliability tests in terms of temperature cycling between −40°C and 125°C with a dwell time of 15 minutes and a ramp rate of 110°C/min. The test chip used for this extensive reliability test had a pitch of 100 μm. Therefore, this work was particularly focused on evaluation on the reliability of ultra fine pitch flip-chip interconnections using anisotropically conductive adhesives on a low-cost substrate. The reliability was characterized by single contact resistance measurement using the four-probe method during temperature cycling testing up to 3000 cycles. The Mean Time To Failure (MTTF) (defined as 50% failure of all tested joints) are 650, 2500, and 3500 cycles when the failure definition is defined as 20% increase, larger than 50 mΩ and larger than 100 mΩ, respectively, using the in-situ electrical resistance measurement technique. Using the discontinuous (manual) measurement at room temperature by taking out the sample from the cycling chamber, the MTTF for the same joint system is around 2500 cycles in the case that the failure criteria is defined as 20% of the resistance increase, far better than the results from the in-situ measurement. The results show clearly that in optimized conditions, high reliability flip-chip anisotropically conductive adhesive joints on low-cost substrate can be achieved.

Flip chip reliability and intermetallic compounds for SIP module

2018 ◽  
Vol 2018 (1) ◽  
pp. 000029-000036 ◽  
Author(s):  
Adrien Morard ◽  
Jean-Christophe Riou ◽  
Gabriel Pares
Keyword(s):  
Flip Chip ◽  
Mechanical Design ◽  
High Reliability ◽  
3D Models ◽  
Organic Substrate ◽  
Bottom Surface ◽  
Active Components ◽  
Recurrent Functions ◽  
Design Rules ◽  
Test Chips

Abstract In the aeronautical field, the electronic integration roadmaps show that the weight and the volume dedicated to on-board electronics must be reduced by a factor of 4 to 10 compared to the existing ones for the most recurrent functions in the next years. This work is an opening to new technological solutions to increase our ability to save space while improving the overall reliability of the system. The first part of this work is dedicated to the study of “system in package” (SiP) solutions based on different substrates, namely organic or silicon. Generally speaking a SIP is composed by several active and passive components stacked on an interposer. Benchmarks done by our laboratory have demonstrated that in terms of substrate, embedded die technology leads to several advantages compared to 3D TSV or TGV based packaging approaches. The benefits provided by this substrate is the possibility to embed some surface mount technologies (SMT), some bare chips or some integrated passives devices (IPD) banks directly above or below the stacked active components. This way, top and bottom surface of the substrate can be used to integrate several heterogeneous dies side by side while using low profile flip-chip assemblies on the C4 side. Finally, in this kind of 3D architecture, this embedded technology enable a gain of integration, without using costly TSV connections. Substrates of high quality allow a reduction of I/Os interconnection pitches leading to very aggressive integration down to 50μm. Secondly, a 3D stack with 3 levels of components, as described above, leads to 2 or 3 REACH compliant sequential assembly processes, depending of the needs. In order to consider all the solutions for an optimized overall integration with high reliability, this work focuse on the study one simple SIP which includes the top die assembled by flip-chip. For the flip chip hybridization on organic interposers copper pillars technologies will be studied. The objective is to understand in depth the processes and to obtain information on the reliability aspect after thermal cycling stress of the flip chip assembly. Thirdly, we built many silicon test chips with different characteristics with a dedicated daisy chain test vehicle. The different parameters are: chip's thicknesses (50 to 200 μm), chip's sizes (2 to 8 mm), bump structures (diameter), the pitches of the interconnection (from 50 to 250 μm) and the number of interconnection rows. Designs were chosen in order to fit real operational configurations. Moreover, these configurations are interesting to build a comprehensive model in order to understand the failure mechanisms. These chips are then stacked by flip chip on the silicon and on the organic substrate. We are also designing the both configurations of substrates. Only the production of the organics part is outsourced. Fourth, for all assemblies thermos-cycling test results will be evaluated with thermo mechanical simulations done by finite elements. 3D models will take into account the different geometries in order to understand and quantify the various key parameters. The analysis will mainly focus on 3D interconnections. Design rules based on the results will be derivated. The aim is to obtain dimensional criteria based on stress versus deformation responses. Lastly intermetallic formation will be evaluated using EBSD analysis to obtain better understanding of copper pillar failures for this specific bumps size. Issued information's will be exploited for designing the future functional SIP. The ultimate goal of this work is finally to define mechanical design rules that can then be used in functional SiP modules.

Stresses in Area Array Assemblies Subjected to Thermal Cycling

2009 ◽  
Author(s):  
Jordan Roberts ◽  
M. Kaysar Rahim ◽  
Safina Hussain ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
...  
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Temperature Cycling ◽  
Aging Effects ◽  
Area Array ◽  
Die Surface ◽  
Test Chips

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

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